soc/mediatek/mt8192: Add dramc ac timing setting

Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: I10e704868e4cd36a938a669879bb1a8632e73e1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

1 files changed, 972 insertions, 0 deletions

diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_ac_timing.h b/src/soc/mediatek/mt8192/include/soc/dramc_ac_timing.h
new file mode 100644
index 000000000000..f00101a3a993
--- /dev/null
+++ b/src/soc/mediatek/mt8192/include/soc/dramc_ac_timing.h
@@ -0,0 +1,972 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8192_DRAMC_AC_TIMING_H__
+#define __SOC_MEDIATEK_MT8192_DRAMC_AC_TIMING_H__
+
+#include <stdint.h>
+#include <sys/types.h>
+#include <soc/dramc_common_mt8192.h>
+#include <soc/dramc_pi_api.h>
+
+/* Normal Mode and Byte Mode */
+#define AC_TIMING_NUMBER	(DDRFREQ_MAX * 2)
+
+struct ac_timing {
+	u8 cbt_mode, read_dbi;
+	u8 div_mode;
+	u16 freq_group;
+	u16 read_lat, write_lat;
+	u16 dqsinctl, datlat;
+	u16 tras;
+	u16 trp;
+	u16 trpab;
+	u16 trc;
+	u16 trfc;
+	u16 trfcpb;
+	u16 txp;
+	u16 trtp;
+	u16 trcd;
+	u16 twr;
+	u16 twtr;
+	u16 tpbr2pbr;
+	u16 tpbr2act;
+	u16 tr2mrw;
+	u16 tw2mrw;
+	u16 tmrr2mrw;
+	u16 tmrw;
+	u16 tmrd;
+	u16 tmrwckel;
+	u16 tpde;
+	u16 tpdx;
+	u16 tmrri;
+	u16 trrd;
+	u16 trrd_4266;
+	u16 tfaw;
+	u16 tfaw_4266;
+	u16 trtw_odt_off;
+	u16 trtw_odt_on;
+	u16 txrefcnt;
+	u16 tzqcs;
+	u16 xrtw2w_new_mode;
+	u16 xrtw2w_old_mode;
+	u16 xrtw2r_odt_on;
+	u16 xrtw2r_odt_off;
+	u16 xrtr2w_odt_on;
+	u16 xrtr2w_odt_off;
+	u16 xrtr2r_new_mode;
+	u16 xrtr2r_old_mode;
+	u16 tr2mrr;
+	u16 vrcgdis_prdcnt;
+	u16 hwset_mr2_op;
+	u16 hwset_mr13_op;
+	u16 hwset_vrcg_op;
+	u16 trcd_derate;
+	u16 trc_derate;
+	u16 tras_derate;
+	u16 trpab_derate;
+	u16 trp_derate;
+	u16 trrd_derate;
+	u16 trtpd;
+	u16 twtpd;
+	u16 tmrr2w_odt_off;
+	u16 tmrr2w_odt_on;
+	u16 ckeprd;
+	u16 ckelckcnt;
+	u16 zqlat2;
+	u16 tras_05T;
+	u16 trp_05T;
+	u16 trpab_05T;
+	u16 trc_05T;
+	u16 trfc_05T;
+	u16 trfcpb_05T;
+	u16 txp_05T;
+	u16 trtp_05T;
+	u16 trcd_05T;
+	u16 twr_05T;
+	u16 twtr_05T;
+	u16 tpbr2pbr_05T;
+	u16 tpbr2act_05T;
+	u16 tr2mrw_05T;
+	u16 tw2mrw_05T;
+	u16 tmrr2mrw_05T;
+	u16 tmrw_05T;
+	u16 tmrd_05T;
+	u16 tmrwckel_05T;
+	u16 tpde_05T;
+	u16 tpdx_05T;
+	u16 tmrri_05T;
+	u16 trrd_05T;
+	u16 trrd_4266_05T;
+	u16 tfaw_05T;
+	u16 tfaw_4266_05T;
+	u16 trtw_odt_off_05T;
+	u16 trtw_odt_on_05T;
+	u16 trcd_derate_05T;
+	u16 trc_derate_05T;
+	u16 tras_derate_05T;
+	u16 trpab_derate_05T;
+	u16 trp_derate_05T;
+	u16 trrd_derate_05T;
+	u16 trtpd_05T;
+	u16 twtpd_05T;
+};
+
+/* Normal Mode and Byte Mode for each frequency */
+static const struct ac_timing ac_timing_tbl[AC_TIMING_NUMBER] = {
+	{
+		.freq_group = DDRFREQ_2133, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0,
+		.read_lat = 36, .write_lat =  18, .div_mode =  DIV8_MODE,
+		.tras = 14, .tras_05T = 0,
+		.trp = 8, .trp_05T = 1,
+		.trpab = 10, .trpab_05T = 0,
+		.trc = 23, .trc_05T = 0,
+		.trfc = 137, .trfc_05T = 1,
+		.trfcpb = 63, .trfcpb_05T = 0,
+		.txp = 1, .txp_05T = 0,
+		.trtp = 2, .trtp_05T = 1,
+		.trcd = 10, .trcd_05T = 0,
+		.twr = 15, .twr_05T = 0,
+		.twtr = 10, .twtr_05T = 1,
+		.tpbr2pbr = 41, .tpbr2pbr_05T = 0,
+		.tpbr2act = 0, .tpbr2act_05T = 0,
+		.tr2mrw = 17, .tr2mrw_05T = 0,
+		.tw2mrw = 11, .tw2mrw_05T = 0,
+		.tmrr2mrw = 14, .tmrr2mrw_05T = 0,
+		.tmrw = 6, .tmrw_05T = 0,
+		.tmrd = 8, .tmrd_05T = 0,
+		.tmrwckel = 9, .tmrwckel_05T = 0,
+		.tpde = 1, .tpde_05T = 1,
+		.tpdx = 1, .tpdx_05T = 0,
+		.tmrri = 14, .tmrri_05T = 0,
+		.trrd = 4, .trrd_05T = 1,
+		.trrd_4266 = 3, .trrd_4266_05T = 0,
+		.tfaw = 13, .tfaw_05T = 1,
+		.tfaw_4266 = 8, .tfaw_4266_05T = 0,
+		.trtw_odt_off = 6, .trtw_odt_off_05T = 0,
+		.trtw_odt_on = 8, .trtw_odt_on_05T = 0,
+		.txrefcnt = 154,
+		.tzqcs = 46,
+		.xrtw2w_new_mode = 5,
+		.xrtw2w_old_mode = 6,
+		.xrtw2r_odt_on = 1,
+		.xrtw2r_odt_off = 1,
+		.xrtr2w_odt_on = 7,
+		.xrtr2w_odt_off = 7,
+		.xrtr2r_new_mode = 3,
+		.xrtr2r_old_mode = 7,
+		.tr2mrr = 4,
+		.vrcgdis_prdcnt = 54,
+		.hwset_mr2_op = 63,
+		.hwset_mr13_op = 216,
+		.hwset_vrcg_op = 208,
+		.trcd_derate = 11, .trcd_derate_05T = 0,
+		.trc_derate = 26, .trc_derate_05T = 0,
+		.tras_derate = 15, .tras_derate_05T = 0,
+		.trpab_derate = 11, .trpab_derate_05T = 0,
+		.trp_derate = 9, .trp_derate_05T = 1,
+		.trrd_derate = 5, .trrd_derate_05T = 1,
+		.trtpd = 14, .trtpd_05T = 1,
+		.twtpd = 18, .twtpd_05T = 0,
+		.tmrr2w_odt_off = 10,
+		.tmrr2w_odt_on = 12,
+		.ckeprd = 3,
+		.ckelckcnt = 3,
+		.zqlat2 = 16,
+		.dqsinctl = 7, .datlat = 18
+	},
+	{
+		.freq_group = DDRFREQ_2133, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0,
+		.read_lat = 40, .write_lat =  18, .div_mode =  DIV8_MODE,
+		.tras = 14, .tras_05T = 0,
+		.trp = 8, .trp_05T = 1,
+		.trpab = 10, .trpab_05T = 0,
+		.trc = 23, .trc_05T = 0,
+		.trfc = 137, .trfc_05T = 1,
+		.trfcpb = 63, .trfcpb_05T = 0,
+		.txp = 1, .txp_05T = 0,
+		.trtp = 2, .trtp_05T = 1,
+		.trcd = 10, .trcd_05T = 0,
+		.twr = 16, .twr_05T = 0,
+		.twtr = 11, .twtr_05T = 1,
+		.tpbr2pbr = 41, .tpbr2pbr_05T = 0,
+		.tpbr2act = 0, .tpbr2act_05T = 0,
+		.tr2mrw = 18, .tr2mrw_05T = 0,
+		.tw2mrw = 11, .tw2mrw_05T = 0,
+		.tmrr2mrw = 15, .tmrr2mrw_05T = 0,
+		.tmrw = 6, .tmrw_05T = 0,
+		.tmrd = 8, .tmrd_05T = 0,
+		.tmrwckel = 9, .tmrwckel_05T = 0,
+		.tpde = 1, .tpde_05T = 1,
+		.tpdx = 1, .tpdx_05T = 0,
+		.tmrri = 14, .tmrri_05T = 0,
+		.trrd = 4, .trrd_05T = 1,
+		.trrd_4266 = 3, .trrd_4266_05T = 0,
+		.tfaw = 13, .tfaw_05T = 1,
+		.tfaw_4266 = 8, .tfaw_4266_05T = 0,
+		.trtw_odt_off = 7, .trtw_odt_off_05T = 0,
+		.trtw_odt_on = 9, .trtw_odt_on_05T = 0,
+		.txrefcnt = 154,
+		.tzqcs = 46,
+		.xrtw2w_new_mode = 5,
+		.xrtw2w_old_mode = 6,
+		.xrtw2r_odt_on = 1,
+		.xrtw2r_odt_off = 1,
+		.xrtr2w_odt_on = 8,
+		.xrtr2w_odt_off = 8,
+		.xrtr2r_new_mode = 3,
+		.xrtr2r_old_mode = 7,
+		.tr2mrr = 4,
+		.vrcgdis_prdcnt = 54,
+		.hwset_mr2_op = 63,
+		.hwset_mr13_op = 216,
+		.hwset_vrcg_op = 208,
+		.trcd_derate = 11, .trcd_derate_05T = 0,
+		.trc_derate = 26, .trc_derate_05T = 0,
+		.tras_derate = 15, .tras_derate_05T = 0,
+		.trpab_derate = 11, .trpab_derate_05T = 0,
+		.trp_derate = 9, .trp_derate_05T = 1,
+		.trrd_derate = 5, .trrd_derate_05T = 1,
+		.trtpd = 15, .trtpd_05T = 1,
+		.twtpd = 19, .twtpd_05T = 0,
+		.tmrr2w_odt_off = 11,
+		.tmrr2w_odt_on = 13,
+		.ckeprd = 3,
+		.ckelckcnt = 3,
+		.zqlat2 = 16,
+		.dqsinctl = 7, .datlat = 18
+	},
+	{
+		.freq_group = DDRFREQ_1600, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0,
+		.read_lat = 28, .write_lat =  14, .div_mode =  DIV8_MODE,
+		.tras = 8, .tras_05T = 1,
+		.trp = 6, .trp_05T = 0,
+		.trpab = 7, .trpab_05T = 0,
+		.trc = 15, .trc_05T = 0,
+		.trfc = 100, .trfc_05T = 0,
+		.trfcpb = 44, .trfcpb_05T = 0,
+		.txp = 0, .txp_05T = 0,
+		.trtp = 1, .trtp_05T = 1,
+		.trcd = 7, .trcd_05T = 1,
+		.twr = 12, .twr_05T = 1,
+		.twtr = 7, .twtr_05T = 0,
+		.tpbr2pbr = 29, .tpbr2pbr_05T = 0,
+		.tpbr2act = 0, .tpbr2act_05T = 0,
+		.tr2mrw = 13, .tr2mrw_05T = 1,
+		.tw2mrw = 9, .tw2mrw_05T = 0,
+		.tmrr2mrw = 11, .tmrr2mrw_05T = 1,
+		.tmrw = 4, .tmrw_05T = 1,
+		.tmrd = 6, .tmrd_05T = 1,
+		.tmrwckel = 7, .tmrwckel_05T = 1,
+		.tpde = 1, .tpde_05T = 1,
+		.tpdx = 1, .tpdx_05T = 0,
+		.tmrri = 10, .tmrri_05T = 1,
+		.trrd = 3, .trrd_05T = 0,
+		.trrd_4266 = 2, .trrd_4266_05T = 0,
+		.tfaw = 8, .tfaw_05T = 0,
+		.tfaw_4266 = 4, .tfaw_4266_05T = 0,
+		.trtw_odt_off = 4, .trtw_odt_off_05T = 0,
+		.trtw_odt_on = 6, .trtw_odt_on_05T = 0,
+		.txrefcnt = 115,
+		.tzqcs = 34,
+		.xrtw2w_new_mode = 4,
+		.xrtw2w_old_mode = 6,
+		.xrtw2r_odt_on = 1,
+		.xrtw2r_odt_off = 1,
+		.xrtr2w_odt_on = 5,
+		.xrtr2w_odt_off = 5,
+		.xrtr2r_new_mode = 3,
+		.xrtr2r_old_mode = 7,
+		.tr2mrr = 4,
+		.vrcgdis_prdcnt = 40,
+		.hwset_mr2_op = 45,
+		.hwset_mr13_op = 216,
+		.hwset_vrcg_op = 208,
+		.trcd_derate = 8, .trcd_derate_05T = 0,
+		.trc_derate = 17, .trc_derate_05T = 0,
+		.tras_derate = 9, .tras_derate_05T = 1,
+		.trpab_derate = 8, .trpab_derate_05T = 0,
+		.trp_derate = 6, .trp_derate_05T = 1,
+		.trrd_derate = 4, .trrd_derate_05T = 0,
+		.trtpd = 12, .trtpd_05T = 0,
+		.twtpd = 14, .twtpd_05T = 1,
+		.tmrr2w_odt_off = 8,
+		.tmrr2w_odt_on = 10,
+		.ckeprd = 2,
+		.ckelckcnt = 2,
+		.zqlat2 = 12,
+		.dqsinctl = 5, .datlat = 15
+	},
+	{
+		.freq_group = DDRFREQ_1600, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0,
+		.read_lat = 32, .write_lat =  14, .div_mode =  DIV8_MODE,
+		.tras = 8, .tras_05T = 1,
+		.trp = 6, .trp_05T = 0,
+		.trpab = 7, .trpab_05T = 0,
+		.trc = 15, .trc_05T = 0,
+		.trfc = 100, .trfc_05T = 0,
+		.trfcpb = 44, .trfcpb_05T = 0,
+		.txp = 0, .txp_05T = 0,
+		.trtp = 1, .trtp_05T = 1,
+		.trcd = 7, .trcd_05T = 1,
+		.twr = 12, .twr_05T = 1,
+		.twtr = 8, .twtr_05T = 0,
+		.tpbr2pbr = 29, .tpbr2pbr_05T = 0,
+		.tpbr2act = 0, .tpbr2act_05T = 0,
+		.tr2mrw = 14, .tr2mrw_05T = 1,
+		.tw2mrw = 9, .tw2mrw_05T = 0,
+		.tmrr2mrw = 12, .tmrr2mrw_05T = 1,
+		.tmrw = 4, .tmrw_05T = 1,
+		.tmrd = 6, .tmrd_05T = 1,
+		.tmrwckel = 7, .tmrwckel_05T = 1,
+		.tpde = 1, .tpde_05T = 1,
+		.tpdx = 1, .tpdx_05T = 0,
+		.tmrri = 10, .tmrri_05T = 1,
+		.trrd = 3, .trrd_05T = 0,
+		.trrd_4266 = 2, .trrd_4266_05T = 0,
+		.tfaw = 8, .tfaw_05T = 0,
+		.tfaw_4266 = 4, .tfaw_4266_05T = 0,
+		.trtw_odt_off = 5, .trtw_odt_off_05T = 0,
+		.trtw_odt_on = 7, .trtw_odt_on_05T = 0,
+		.txrefcnt = 115,
+		.tzqcs = 34,
+		.xrtw2w_new_mode = 4,
+		.xrtw2w_old_mode = 6,
+		.xrtw2r_odt_on = 1,
+		.xrtw2r_odt_off = 1,
+		.xrtr2w_odt_on = 6,
+		.xrtr2w_odt_off = 6,
+		.xrtr2r_new_mode = 3,
+		.xrtr2r_old_mode = 7,
+		.tr2mrr = 4,
+		.vrcgdis_prdcnt = 40,
+		.hwset_mr2_op = 45,
+		.hwset_mr13_op = 216,
+		.hwset_vrcg_op = 208,
+		.trcd_derate = 8, .trcd_derate_05T = 0,
+		.trc_derate = 17, .trc_derate_05T = 0,
+		.tras_derate = 9, .tras_derate_05T = 1,
+		.trpab_derate = 8, .trpab_derate_05T = 0,
+		.trp_derate = 6, .trp_derate_05T = 1,
+		.trrd_derate = 4, .trrd_derate_05T = 0,
+		.trtpd = 13, .trtpd_05T = 0,
+		.twtpd = 15, .twtpd_05T = 1,
+		.tmrr2w_odt_off = 9,
+		.tmrr2w_odt_on = 11,
+		.ckeprd = 2,
+		.ckelckcnt = 2,
+		.zqlat2 = 12,
+		.dqsinctl = 5, .datlat = 15
+	},
+	{
+		.freq_group = DDRFREQ_1200, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0,
+		.read_lat = 24, .write_lat =  12, .div_mode =  DIV8_MODE,
+		.tras = 4, .tras_05T = 1,
+		.trp = 4, .trp_05T = 0,
+		.trpab = 5, .trpab_05T = 0,
+		.trc = 9, .trc_05T = 1,
+		.trfc = 72, .trfc_05T = 1,
+		.trfcpb = 30, .trfcpb_05T = 1,
+		.txp = 0, .txp_05T = 1,
+		.trtp = 1, .trtp_05T = 0,
+		.trcd = 5, .trcd_05T = 1,
+		.twr = 9, .twr_05T = 1,
+		.twtr = 6, .twtr_05T = 1,
+		.tpbr2pbr = 20, .tpbr2pbr_05T = 1,
+		.tpbr2act = 0, .tpbr2act_05T = 0,
+		.tr2mrw = 12, .tr2mrw_05T = 0,
+		.tw2mrw = 8, .tw2mrw_05T = 0,
+		.tmrr2mrw = 10, .tmrr2mrw_05T = 0,
+		.tmrw = 4, .tmrw_05T = 0,
+		.tmrd = 5, .tmrd_05T = 0,
+		.tmrwckel = 6, .tmrwckel_05T = 0,
+		.tpde = 1, .tpde_05T = 1,
+		.tpdx = 1, .tpdx_05T = 0,
+		.tmrri = 8, .tmrri_05T = 0,
+		.trrd = 2, .trrd_05T = 1,
+		.trrd_4266 = 1, .trrd_4266_05T = 1,
+		.tfaw = 4, .tfaw_05T = 1,
+		.tfaw_4266 = 1, .tfaw_4266_05T = 1,
+		.trtw_odt_off = 3, .trtw_odt_off_05T = 0,
+		.trtw_odt_on = 6, .trtw_odt_on_05T = 0,
+		.txrefcnt = 87,
+		.tzqcs = 26,
+		.xrtw2w_new_mode = 4,
+		.xrtw2w_old_mode = 6,
+		.xrtw2r_odt_on = 2,
+		.xrtw2r_odt_off = 2,
+		.xrtr2w_odt_on = 5,
+		.xrtr2w_odt_off = 5,
+		.xrtr2r_new_mode = 3,
+		.xrtr2r_old_mode = 6,
+		.tr2mrr = 4,
+		.vrcgdis_prdcnt = 31,
+		.hwset_mr2_op = 36,
+		.hwset_mr13_op = 24,
+		.hwset_vrcg_op = 16,
+		.trcd_derate = 6, .trcd_derate_05T = 0,
+		.trc_derate = 10, .trc_derate_05T = 1,
+		.tras_derate = 5, .tras_derate_05T = 0,
+		.trpab_derate = 5, .trpab_derate_05T = 1,
+		.trp_derate = 4, .trp_derate_05T = 1,
+		.trrd_derate = 3, .trrd_derate_05T = 0,
+		.trtpd = 10, .trtpd_05T = 1,
+		.twtpd = 12, .twtpd_05T = 0,
+		.tmrr2w_odt_off = 6,
+		.tmrr2w_odt_on = 8,
+		.ckeprd = 2,
+		.ckelckcnt = 2,
+		.zqlat2 = 10,
+		.dqsinctl = 4, .datlat = 13
+	},
+	{
+		.freq_group = DDRFREQ_1200, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0,
+		.read_lat = 26, .write_lat =  12, .div_mode =  DIV8_MODE,
+		.tras = 4, .tras_05T = 1,
+		.trp = 4, .trp_05T = 0,
+		.trpab = 5, .trpab_05T = 0,
+		.trc = 9, .trc_05T = 1,
+		.trfc = 72, .trfc_05T = 1,
+		.trfcpb = 30, .trfcpb_05T = 1,
+		.txp = 0, .txp_05T = 1,
+		.trtp = 1, .trtp_05T = 0,
+		.trcd = 5, .trcd_05T = 1,
+		.twr = 10, .twr_05T = 0,
+		.twtr = 6, .twtr_05T = 0,
+		.tpbr2pbr = 20, .tpbr2pbr_05T = 1,
+		.tpbr2act = 0, .tpbr2act_05T = 0,
+		.tr2mrw = 12, .tr2mrw_05T = 1,
+		.tw2mrw = 8, .tw2mrw_05T = 0,
+		.tmrr2mrw = 10, .tmrr2mrw_05T = 1,
+		.tmrw = 4, .tmrw_05T = 0,
+		.tmrd = 5, .tmrd_05T = 0,
+		.tmrwckel = 6, .tmrwckel_05T = 0,
+		.tpde = 1, .tpde_05T = 1,
+		.tpdx = 1, .tpdx_05T = 0,
+		.tmrri = 8, .tmrri_05T = 0,
+		.trrd = 2, .trrd_05T = 1,
+		.trrd_4266 = 1, .trrd_4266_05T = 1,
+		.tfaw = 4, .tfaw_05T = 1,
+		.tfaw_4266 = 1, .tfaw_4266_05T = 1,
+		.trtw_odt_off = 4, .trtw_odt_off_05T = 0,
+		.trtw_odt_on = 6, .trtw_odt_on_05T = 0,
+		.txrefcnt = 87,
+		.tzqcs = 26,
+		.xrtw2w_new_mode = 4,
+		.xrtw2w_old_mode = 6,
+		.xrtw2r_odt_on = 1,
+		.xrtw2r_odt_off = 1,
+		.xrtr2w_odt_on = 5,
+		.xrtr2w_odt_off = 5,
+		.xrtr2r_new_mode = 3,
+		.xrtr2r_old_mode = 6,
+		.tr2mrr = 4,
+		.vrcgdis_prdcnt = 31,
+		.hwset_mr2_op = 36,
+		.hwset_mr13_op = 24,
+		.hwset_vrcg_op = 16,
+		.trcd_derate = 6, .trcd_derate_05T = 0,
+		.trc_derate = 10, .trc_derate_05T = 1,
+		.tras_derate = 5, .tras_derate_05T = 0,
+		.trpab_derate = 5, .trpab_derate_05T = 1,
+		.trp_derate = 4, .trp_derate_05T = 1,
+		.trrd_derate = 3, .trrd_derate_05T = 0,
+		.trtpd = 11, .trtpd_05T = 0,
+		.twtpd = 13, .twtpd_05T = 0,
+		.tmrr2w_odt_off = 7,
+		.tmrr2w_odt_on = 9,
+		.ckeprd = 2,
+		.ckelckcnt = 2,
+		.zqlat2 = 10,
+		.dqsinctl = 4, .datlat = 13
+	},
+	{
+		.freq_group = DDRFREQ_933, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0,
+		.read_lat = 20, .write_lat =  10, .div_mode =  DIV8_MODE,
+		.tras = 1, .tras_05T = 1,
+		.trp = 3, .trp_05T = 0,
+		.trpab = 3, .trpab_05T = 1,
+		.trc = 5, .trc_05T = 0,
+		.trfc = 53, .trfc_05T = 1,
+		.trfcpb = 21, .trfcpb_05T = 0,
+		.txp = 0, .txp_05T = 0,
+		.trtp = 0, .trtp_05T = 1,
+		.trcd = 4, .trcd_05T = 1,
+		.twr = 8, .twr_05T = 1,
+		.twtr = 5, .twtr_05T = 1,
+		.tpbr2pbr = 14, .tpbr2pbr_05T = 0,
+		.tpbr2act = 0, .tpbr2act_05T = 0,
+		.tr2mrw = 10, .tr2mrw_05T = 0,
+		.tw2mrw = 7, .tw2mrw_05T = 0,
+		.tmrr2mrw = 9, .tmrr2mrw_05T = 0,
+		.tmrw = 3, .tmrw_05T = 0,
+		.tmrd = 4, .tmrd_05T = 0,
+		.tmrwckel = 5, .tmrwckel_05T = 0,
+		.tpde = 1, .tpde_05T = 1,
+		.tpdx = 1, .tpdx_05T = 0,
+		.tmrri = 6, .tmrri_05T = 0,
+		.trrd = 1, .trrd_05T = 1,
+		.trrd_4266 = 1, .trrd_4266_05T = 0,
+		.tfaw = 1, .tfaw_05T = 1,
+		.tfaw_4266 = 0, .tfaw_4266_05T = 0,
+		.trtw_odt_off = 3, .trtw_odt_off_05T = 0,
+		.trtw_odt_on = 5, .trtw_odt_on_05T = 0,
+		.txrefcnt = 68,
+		.tzqcs = 19,
+		.xrtw2w_new_mode = 4,
+		.xrtw2w_old_mode = 6,
+		.xrtw2r_odt_on = 2,
+		.xrtw2r_odt_off = 2,
+		.xrtr2w_odt_on = 3,
+		.xrtr2w_odt_off = 3,
+		.xrtr2r_new_mode = 3,
+		.xrtr2r_old_mode = 6,
+		.tr2mrr = 4,
+		.vrcgdis_prdcnt = 24,
+		.hwset_mr2_op = 27,
+		.hwset_mr13_op = 24,
+		.hwset_vrcg_op = 16,
+		.trcd_derate = 5, .trcd_derate_05T = 0,
+		.trc_derate = 6, .trc_derate_05T = 1,
+		.tras_derate = 2, .tras_derate_05T = 0,
+		.trpab_derate = 4, .trpab_derate_05T = 0,
+		.trp_derate = 3, .trp_derate_05T = 1,
+		.trrd_derate = 2, .trrd_derate_05T = 0,
+		.trtpd = 9, .trtpd_05T = 1,
+		.twtpd = 10, .twtpd_05T = 1,
+		.tmrr2w_odt_off = 5,
+		.tmrr2w_odt_on = 7,
+		.ckeprd = 1,
+		.ckelckcnt = 2,
+		.zqlat2 = 7,
+		.dqsinctl = 3, .datlat = 13
+	},
+	{
+		.freq_group = DDRFREQ_933, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0,
+		.read_lat = 22, .write_lat =  10, .div_mode =  DIV8_MODE,
+		.tras = 1, .tras_05T = 1,
+		.trp = 3, .trp_05T = 0,
+		.trpab = 3, .trpab_05T = 1,
+		.trc = 5, .trc_05T = 0,
+		.trfc = 53, .trfc_05T = 1,
+		.trfcpb = 21, .trfcpb_05T = 0,
+		.txp = 0, .txp_05T = 0,
+		.trtp = 0, .trtp_05T = 1,
+		.trcd = 4, .trcd_05T = 1,
+		.twr = 8, .twr_05T = 0,
+		.twtr = 5, .twtr_05T = 0,
+		.tpbr2pbr = 14, .tpbr2pbr_05T = 0,
+		.tpbr2act = 0, .tpbr2act_05T = 0,
+		.tr2mrw = 10, .tr2mrw_05T = 1,
+		.tw2mrw = 7, .tw2mrw_05T = 0,
+		.tmrr2mrw = 9, .tmrr2mrw_05T = 1,
+		.tmrw = 3, .tmrw_05T = 0,
+		.tmrd = 4, .tmrd_05T = 0,
+		.tmrwckel = 5, .tmrwckel_05T = 0,
+		.tpde = 1, .tpde_05T = 1,
+		.tpdx = 1, .tpdx_05T = 0,
+		.tmrri = 6, .tmrri_05T = 0,
+		.trrd = 1, .trrd_05T = 1,
+		.trrd_4266 = 1, .trrd_4266_05T = 0,
+		.tfaw = 1, .tfaw_05T = 1,
+		.tfaw_4266 = 0, .tfaw_4266_05T = 0,
+		.trtw_odt_off = 3, .trtw_odt_off_05T = 0,
+		.trtw_odt_on = 5, .trtw_odt_on_05T = 0,
+		.txrefcnt = 68,
+		.tzqcs = 19,
+		.xrtw2w_new_mode = 4,
+		.xrtw2w_old_mode = 6,
+		.xrtw2r_odt_on = 2,
+		.xrtw2r_odt_off = 1,
+		.xrtr2w_odt_on = 4,
+		.xrtr2w_odt_off = 4,
+		.xrtr2r_new_mode = 3,
+		.xrtr2r_old_mode = 6,
+		.tr2mrr = 4,
+		.vrcgdis_prdcnt = 24,
+		.hwset_mr2_op = 27,
+		.hwset_mr13_op = 24,
+		.hwset_vrcg_op = 16,
+		.trcd_derate = 5, .trcd_derate_05T = 0,
+		.trc_derate = 6, .trc_derate_05T = 1,
+		.tras_derate = 2, .tras_derate_05T = 0,
+		.trpab_derate = 4, .trpab_derate_05T = 0,
+		.trp_derate = 3, .trp_derate_05T = 1,
+		.trrd_derate = 2, .trrd_derate_05T = 0,
+		.trtpd = 10, .trtpd_05T = 0,
+		.twtpd = 11, .twtpd_05T = 0,
+		.tmrr2w_odt_off = 6,
+		.tmrr2w_odt_on = 8,
+		.ckeprd = 1,
+		.ckelckcnt = 2,
+		.zqlat2 = 7,
+		.dqsinctl = 3, .datlat = 13
+	},
+	{
+		.freq_group = DDRFREQ_800, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0,
+		.read_lat = 14, .write_lat =  8, .div_mode =  DIV8_MODE,
+		.tras = 0, .tras_05T = 0,
+		.trp = 2, .trp_05T = 1,
+		.trpab = 3, .trpab_05T = 0,
+		.trc = 3, .trc_05T = 0,
+		.trfc = 44, .trfc_05T = 0,
+		.trfcpb = 16, .trfcpb_05T = 0,
+		.txp = 0, .txp_05T = 0,
+		.trtp = 0, .trtp_05T = 1,
+		.trcd = 4, .trcd_05T = 0,
+		.twr = 7, .twr_05T = 1,
+		.twtr = 4, .twtr_05T = 1,
+		.tpbr2pbr = 11, .tpbr2pbr_05T = 0,
+		.tpbr2act = 0, .tpbr2act_05T = 0,
+		.tr2mrw = 8, .tr2mrw_05T = 1,
+		.tw2mrw = 6, .tw2mrw_05T = 1,
+		.tmrr2mrw = 7, .tmrr2mrw_05T = 0,
+		.tmrw = 3, .tmrw_05T = 0,
+		.tmrd = 3, .tmrd_05T = 1,
+		.tmrwckel = 4, .tmrwckel_05T = 1,
+		.tpde = 1, .tpde_05T = 1,
+		.tpdx = 1, .tpdx_05T = 0,
+		.tmrri = 5, .tmrri_05T = 1,
+		.trrd = 1, .trrd_05T = 0,
+		.trrd_4266 = 0, .trrd_4266_05T = 1,
+		.tfaw = 0, .tfaw_05T = 0,
+		.tfaw_4266 = 0, .tfaw_4266_05T = 0,
+		.trtw_odt_off = 1, .trtw_odt_off_05T = 0,
+		.trtw_odt_on = 4, .trtw_odt_on_05T = 0,
+		.txrefcnt = 58,
+		.tzqcs = 16,
+		.xrtw2w_new_mode = 4,
+		.xrtw2w_old_mode = 6,
+		.xrtw2r_odt_on = 3,
+		.xrtw2r_odt_off = 3,
+		.xrtr2w_odt_on = 3,
+		.xrtr2w_odt_off = 3,
+		.xrtr2r_new_mode = 3,
+		.xrtr2r_old_mode = 6,
+		.tr2mrr = 4,
+		.vrcgdis_prdcnt = 20,
+		.hwset_mr2_op = 18,
+		.hwset_mr13_op = 24,
+		.hwset_vrcg_op = 16,
+		.trcd_derate = 4, .trcd_derate_05T = 0,
+		.trc_derate = 4, .trc_derate_05T = 0,
+		.tras_derate = 0, .tras_derate_05T = 1,
+		.trpab_derate = 3, .trpab_derate_05T = 1,
+		.trp_derate = 2, .trp_derate_05T = 1,
+		.trrd_derate = 1, .trrd_derate_05T = 1,
+		.trtpd = 7, .trtpd_05T = 1,
+		.twtpd = 9, .twtpd_05T = 1,
+		.tmrr2w_odt_off = 3,
+		.tmrr2w_odt_on = 5,
+		.ckeprd = 1,
+		.ckelckcnt = 2,
+		.zqlat2 = 6,
+		.dqsinctl = 2, .datlat = 10
+	},
+	{
+		.freq_group = DDRFREQ_800, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0,
+		.read_lat = 16, .write_lat =  8, .div_mode =  DIV8_MODE,
+		.tras = 0, .tras_05T = 0,
+		.trp = 2, .trp_05T = 1,
+		.trpab = 3, .trpab_05T = 0,
+		.trc = 3, .trc_05T = 0,
+		.trfc = 44, .trfc_05T = 0,
+		.trfcpb = 16, .trfcpb_05T = 0,
+		.txp = 0, .txp_05T = 0,
+		.trtp = 0, .trtp_05T = 1,
+		.trcd = 4, .trcd_05T = 0,
+		.twr = 7, .twr_05T = 0,
+		.twtr = 4, .twtr_05T = 0,
+		.tpbr2pbr = 11, .tpbr2pbr_05T = 0,
+		.tpbr2act = 0, .tpbr2act_05T = 0,
+		.tr2mrw = 9, .tr2mrw_05T = 0,
+		.tw2mrw = 6, .tw2mrw_05T = 1,
+		.tmrr2mrw = 7, .tmrr2mrw_05T = 1,
+		.tmrw = 3, .tmrw_05T = 0,
+		.tmrd = 3, .tmrd_05T = 1,
+		.tmrwckel = 4, .tmrwckel_05T = 1,
+		.tpde = 1, .tpde_05T = 1,
+		.tpdx = 1, .tpdx_05T = 0,
+		.tmrri = 5, .tmrri_05T = 1,
+		.trrd = 1, .trrd_05T = 0,
+		.trrd_4266 = 0, .trrd_4266_05T = 1,
+		.tfaw = 0, .tfaw_05T = 0,
+		.tfaw_4266 = 0, .tfaw_4266_05T = 0,
+		.trtw_odt_off = 2, .trtw_odt_off_05T = 0,
+		.trtw_odt_on = 4, .trtw_odt_on_05T = 0,
+		.txrefcnt = 58,
+		.tzqcs = 16,
+		.xrtw2w_new_mode = 4,
+		.xrtw2w_old_mode = 6,
+		.xrtw2r_odt_on = 3,
+		.xrtw2r_odt_off = 2,
+		.xrtr2w_odt_on = 3,
+		.xrtr2w_odt_off = 3,
+		.xrtr2r_new_mode = 3,
+		.xrtr2r_old_mode = 6,
+		.tr2mrr = 4,
+		.vrcgdis_prdcnt = 20,
+		.hwset_mr2_op = 18,
+		.hwset_mr13_op = 24,
+		.hwset_vrcg_op = 16,
+		.trcd_derate = 4, .trcd_derate_05T = 0,
+		.trc_derate = 4, .trc_derate_05T = 0,
+		.tras_derate = 0, .tras_derate_05T = 1,
+		.trpab_derate = 3, .trpab_derate_05T = 1,
+		.trp_derate = 2, .trp_derate_05T = 1,
+		.trrd_derate = 1, .trrd_derate_05T = 1,
+		.trtpd = 8, .trtpd_05T = 0,
+		.twtpd = 9, .twtpd_05T = 1,
+		.tmrr2w_odt_off = 4,
+		.tmrr2w_odt_on = 6,
+		.ckeprd = 1,
+		.ckelckcnt = 2,
+		.zqlat2 = 6,
+		.dqsinctl = 2, .datlat = 10
+	},
+	{
+		.freq_group = DDRFREQ_600, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0,
+		.read_lat = 14, .write_lat =  8, .div_mode =  DIV8_MODE,
+		.tras = 0, .tras_05T = 0,
+		.trp = 1, .trp_05T = 1,
+		.trpab = 2, .trpab_05T = 0,
+		.trc = 0, .trc_05T = 1,
+		.trfc = 30, .trfc_05T = 1,
+		.trfcpb = 9, .trfcpb_05T = 1,
+		.txp = 0, .txp_05T = 0,
+		.trtp = 0, .trtp_05T = 1,
+		.trcd = 3, .trcd_05T = 0,
+		.twr = 6, .twr_05T = 1,
+		.twtr = 4, .twtr_05T = 1,
+		.tpbr2pbr = 7, .tpbr2pbr_05T = 0,
+		.tpbr2act = 0, .tpbr2act_05T = 0,
+		.tr2mrw = 8, .tr2mrw_05T = 1,
+		.tw2mrw = 6, .tw2mrw_05T = 1,
+		.tmrr2mrw = 7, .tmrr2mrw_05T = 0,
+		.tmrw = 3, .tmrw_05T = 0,
+		.tmrd = 3, .tmrd_05T = 0,
+		.tmrwckel = 4, .tmrwckel_05T = 0,
+		.tpde = 1, .tpde_05T = 1,
+		.tpdx = 1, .tpdx_05T = 0,
+		.tmrri = 4, .tmrri_05T = 0,
+		.trrd = 1, .trrd_05T = 0,
+		.trrd_4266 = 0, .trrd_4266_05T = 1,
+		.tfaw = 0, .tfaw_05T = 0,
+		.tfaw_4266 = 0, .tfaw_4266_05T = 0,
+		.trtw_odt_off = 1, .trtw_odt_off_05T = 0,
+		.trtw_odt_on = 4, .trtw_odt_on_05T = 0,
+		.txrefcnt = 44,
+		.tzqcs = 12,
+		.xrtw2w_new_mode = 4,
+		.xrtw2w_old_mode = 6,
+		.xrtw2r_odt_on = 3,
+		.xrtw2r_odt_off = 3,
+		.xrtr2w_odt_on = 3,
+		.xrtr2w_odt_off = 3,
+		.xrtr2r_new_mode = 3,
+		.xrtr2r_old_mode = 6,
+		.tr2mrr = 4,
+		.vrcgdis_prdcnt = 16,
+		.hwset_mr2_op = 18,
+		.hwset_mr13_op = 24,
+		.hwset_vrcg_op = 16,
+		.trcd_derate = 3, .trcd_derate_05T = 0,
+		.trc_derate = 1, .trc_derate_05T = 0,
+		.tras_derate = 0, .tras_derate_05T = 0,
+		.trpab_derate = 2, .trpab_derate_05T = 0,
+		.trp_derate = 1, .trp_derate_05T = 1,
+		.trrd_derate = 1, .trrd_derate_05T = 0,
+		.trtpd = 7, .trtpd_05T = 1,
+		.twtpd = 8, .twtpd_05T = 1,
+		.tmrr2w_odt_off = 3,
+		.tmrr2w_odt_on = 5,
+		.ckeprd = 1,
+		.ckelckcnt = 2,
+		.zqlat2 = 5,
+		.dqsinctl = 2, .datlat = 9
+	},
+	{
+		.freq_group = DDRFREQ_600, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0,
+		.read_lat = 16, .write_lat =  8, .div_mode =  DIV8_MODE,
+		.tras = 0, .tras_05T = 0,
+		.trp = 1, .trp_05T = 1,
+		.trpab = 2, .trpab_05T = 0,
+		.trc = 0, .trc_05T = 1,
+		.trfc = 30, .trfc_05T = 1,
+		.trfcpb = 9, .trfcpb_05T = 1,
+		.txp = 0, .txp_05T = 0,
+		.trtp = 0, .trtp_05T = 1,
+		.trcd = 3, .trcd_05T = 0,
+		.twr = 6, .twr_05T = 0,
+		.twtr = 4, .twtr_05T = 1,
+		.tpbr2pbr = 7, .tpbr2pbr_05T = 0,
+		.tpbr2act = 0, .tpbr2act_05T = 0,
+		.tr2mrw = 9, .tr2mrw_05T = 0,
+		.tw2mrw = 6, .tw2mrw_05T = 1,
+		.tmrr2mrw = 7, .tmrr2mrw_05T = 1,
+		.tmrw = 3, .tmrw_05T = 0,
+		.tmrd = 3, .tmrd_05T = 0,
+		.tmrwckel = 4, .tmrwckel_05T = 0,
+		.tpde = 1, .tpde_05T = 1,
+		.tpdx = 1, .tpdx_05T = 0,
+		.tmrri = 4, .tmrri_05T = 0,
+		.trrd = 1, .trrd_05T = 0,
+		.trrd_4266 = 0, .trrd_4266_05T = 1,
+		.tfaw = 0, .tfaw_05T = 0,
+		.tfaw_4266 = 0, .tfaw_4266_05T = 0,
+		.trtw_odt_off = 2, .trtw_odt_off_05T = 0,
+		.trtw_odt_on = 5, .trtw_odt_on_05T = 0,
+		.txrefcnt = 44,
+		.tzqcs = 12,
+		.xrtw2w_new_mode = 4,
+		.xrtw2w_old_mode = 6,
+		.xrtw2r_odt_on = 3,
+		.xrtw2r_odt_off = 2,
+		.xrtr2w_odt_on = 3,
+		.xrtr2w_odt_off = 3,
+		.xrtr2r_new_mode = 3,
+		.xrtr2r_old_mode = 6,
+		.tr2mrr = 4,
+		.vrcgdis_prdcnt = 16,
+		.hwset_mr2_op = 18,
+		.hwset_mr13_op = 24,
+		.hwset_vrcg_op = 16,
+		.trcd_derate = 3, .trcd_derate_05T = 0,
+		.trc_derate = 1, .trc_derate_05T = 0,
+		.tras_derate = 0, .tras_derate_05T = 0,
+		.trpab_derate = 2, .trpab_derate_05T = 0,
+		.trp_derate = 1, .trp_derate_05T = 1,
+		.trrd_derate = 1, .trrd_derate_05T = 0,
+		.trtpd = 8, .trtpd_05T = 0,
+		.twtpd = 9, .twtpd_05T = 0,
+		.tmrr2w_odt_off = 4,
+		.tmrr2w_odt_on = 6,
+		.ckeprd = 1,
+		.ckelckcnt = 2,
+		.zqlat2 = 5,
+		.dqsinctl = 2, .datlat = 9
+	},
+	{
+		.freq_group = DDRFREQ_400, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0,
+		.read_lat = 14, .write_lat =  8, .div_mode =  DIV4_MODE,
+		.tras = 1, .tras_05T = 0,
+		.trp = 2, .trp_05T = 0,
+		.trpab = 3, .trpab_05T = 0,
+		.trc = 3, .trc_05T = 0,
+		.trfc = 44, .trfc_05T = 0,
+		.trfcpb = 16, .trfcpb_05T = 0,
+		.txp = 0, .txp_05T = 0,
+		.trtp = 3, .trtp_05T = 0,
+		.trcd = 4, .trcd_05T = 0,
+		.twr = 12, .twr_05T = 0,
+		.twtr = 10, .twtr_05T = 0,
+		.tpbr2pbr = 11, .tpbr2pbr_05T = 0,
+		.tpbr2act = 0, .tpbr2act_05T = 0,
+		.tr2mrw = 16, .tr2mrw_05T = 0,
+		.tw2mrw = 13, .tw2mrw_05T = 0,
+		.tmrr2mrw = 14, .tmrr2mrw_05T = 0,
+		.tmrw = 6, .tmrw_05T = 0,
+		.tmrd = 6, .tmrd_05T = 0,
+		.tmrwckel = 8, .tmrwckel_05T = 0,
+		.tpde = 3, .tpde_05T = 0,
+		.tpdx = 3, .tpdx_05T = 0,
+		.tmrri = 7, .tmrri_05T = 0,
+		.trrd = 1, .trrd_05T = 0,
+		.trrd_4266 = 1, .trrd_4266_05T = 0,
+		.tfaw = 0, .tfaw_05T = 0,
+		.tfaw_4266 = 0, .tfaw_4266_05T = 0,
+		.trtw_odt_off = 6, .trtw_odt_off_05T = 0,
+		.trtw_odt_on = 11, .trtw_odt_on_05T = 0,
+		.txrefcnt = 58,
+		.tzqcs = 16,
+		.xrtw2w_new_mode = 9,
+		.xrtw2w_old_mode = 10,
+		.xrtw2r_odt_on = 7,
+		.xrtw2r_odt_off = 5,
+		.xrtr2w_odt_on = 9,
+		.xrtr2w_odt_off = 9,
+		.xrtr2r_new_mode = 6,
+		.xrtr2r_old_mode = 8,
+		.tr2mrr = 8,
+		.vrcgdis_prdcnt = 20,
+		.hwset_mr2_op = 18,
+		.hwset_mr13_op = 24,
+		.hwset_vrcg_op = 16,
+		.trcd_derate = 4, .trcd_derate_05T = 0,
+		.trc_derate = 4, .trc_derate_05T = 0,
+		.tras_derate = 1, .tras_derate_05T = 0,
+		.trpab_derate = 3, .trpab_derate_05T = 0,
+		.trp_derate = 2, .trp_derate_05T = 0,
+		.trrd_derate = 2, .trrd_derate_05T = 0,
+		.trtpd = 15, .trtpd_05T = 0,
+		.twtpd = 15, .twtpd_05T = 0,
+		.tmrr2w_odt_off = 10,
+		.tmrr2w_odt_on = 12,
+		.ckeprd = 2,
+		.ckelckcnt = 3,
+		.zqlat2 = 6,
+		.dqsinctl = 5, .datlat = 15
+	},
+	{
+		.freq_group = DDRFREQ_400, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0,
+		.read_lat = 16, .write_lat =  8, .div_mode =  DIV4_MODE,
+		.tras = 1, .tras_05T = 0,
+		.trp = 2, .trp_05T = 0,
+		.trpab = 3, .trpab_05T = 0,
+		.trc = 3, .trc_05T = 0,
+		.trfc = 44, .trfc_05T = 0,
+		.trfcpb = 16, .trfcpb_05T = 0,
+		.txp = 0, .txp_05T = 0,
+		.trtp = 3, .trtp_05T = 0,
+		.trcd = 4, .trcd_05T = 0,
+		.twr = 12, .twr_05T = 0,
+		.twtr = 10, .twtr_05T = 0,
+		.tpbr2pbr = 11, .tpbr2pbr_05T = 0,
+		.tpbr2act = 0, .tpbr2act_05T = 0,
+		.tr2mrw = 17, .tr2mrw_05T = 0,
+		.tw2mrw = 13, .tw2mrw_05T = 0,
+		.tmrr2mrw = 15, .tmrr2mrw_05T = 0,
+		.tmrw = 6, .tmrw_05T = 0,
+		.tmrd = 6, .tmrd_05T = 0,
+		.tmrwckel = 8, .tmrwckel_05T = 0,
+		.tpde = 3, .tpde_05T = 0,
+		.tpdx = 3, .tpdx_05T = 0,
+		.tmrri = 7, .tmrri_05T = 0,
+		.trrd = 1, .trrd_05T = 0,
+		.trrd_4266 = 1, .trrd_4266_05T = 0,
+		.tfaw = 0, .tfaw_05T = 0,
+		.tfaw_4266 = 0, .tfaw_4266_05T = 0,
+		.trtw_odt_off = 7, .trtw_odt_off_05T = 0,
+		.trtw_odt_on = 12, .trtw_odt_on_05T = 0,
+		.txrefcnt = 58,
+		.tzqcs = 16,
+		.xrtw2w_new_mode = 9,
+		.xrtw2w_old_mode = 10,
+		.xrtw2r_odt_on = 6,
+		.xrtw2r_odt_off = 4,
+		.xrtr2w_odt_on = 10,
+		.xrtr2w_odt_off = 10,
+		.xrtr2r_new_mode = 6,
+		.xrtr2r_old_mode = 9,
+		.tr2mrr = 8,
+		.vrcgdis_prdcnt = 20,
+		.hwset_mr2_op = 18,
+		.hwset_mr13_op = 24,
+		.hwset_vrcg_op = 16,
+		.trcd_derate = 4, .trcd_derate_05T = 0,
+		.trc_derate = 4, .trc_derate_05T = 0,
+		.tras_derate = 1, .tras_derate_05T = 0,
+		.trpab_derate = 3, .trpab_derate_05T = 0,
+		.trp_derate = 2, .trp_derate_05T = 0,
+		.trrd_derate = 2, .trrd_derate_05T = 0,
+		.trtpd = 16, .trtpd_05T = 0,
+		.twtpd = 15, .twtpd_05T = 0,
+		.tmrr2w_odt_off = 11,
+		.tmrr2w_odt_on = 13,
+		.ckeprd = 2,
+		.ckelckcnt = 3,
+		.zqlat2 = 6,
+		.dqsinctl = 5, .datlat = 15
+	},
+};
+
+#endif  /* __SOC_MEDIATEK_MT8192_DRAMC_AC_TIMING_H__ */