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author | Nina Wu <nina-cm.wu@mediatek.corp-partner.google.com> | 2021-01-21 14:38:23 +0800 |
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committer | Hung-Te Lin <hungte@chromium.org> | 2021-03-15 02:28:32 +0000 |
commit | 31f914c5544ba4fd4f5a4b8cfc09a7657354adcc (patch) | |
tree | 4329c8fb1c5aaae295302a05b4cf12a9f0f57dda /src/soc/mediatek/mt8192 | |
parent | a79d6e76b852e5e5a4667818722388f1a07497df (diff) | |
download | coreboot-31f914c5544ba4fd4f5a4b8cfc09a7657354adcc.tar.gz coreboot-31f914c5544ba4fd4f5a4b8cfc09a7657354adcc.tar.bz2 coreboot-31f914c5544ba4fd4f5a4b8cfc09a7657354adcc.zip |
soc/mediatek/mt8192: devapc: Add domain remap setting
MT8192 devapc supports remapping domains.
There may be different domain bit for different subsys.
For example, domain bit in INFRA is 4-bit, while in MMSYS,
domain bit is 2-bit. For INFRA master to access MM registers,
the domain bit will change from 4 to 2 and need to be remapped.
In this patch we have remapped:
1. TINYSYS (3-bit to 4-bit)
- domain 3 to domain 3
- others to domain 15
2. MMSYS slave (4-bit to 2-bit)
- domain X to domain X, for X = 0 ~ 3
- others to domain 0
Change-Id: Id10a4c0bdf141cc76a386159896c861d0dc302aa
Signed-off-by: Nina Wu <nina-cm.wu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8192')
-rw-r--r-- | src/soc/mediatek/mt8192/devapc.c | 72 | ||||
-rw-r--r-- | src/soc/mediatek/mt8192/include/soc/devapc.h | 18 |
2 files changed, 76 insertions, 14 deletions
diff --git a/src/soc/mediatek/mt8192/devapc.c b/src/soc/mediatek/mt8192/devapc.c index d297d523b182..9e3692e6348d 100644 --- a/src/soc/mediatek/mt8192/devapc.c +++ b/src/soc/mediatek/mt8192/devapc.c @@ -16,6 +16,33 @@ static void infra_master_init(uintptr_t base) SET32_BITFIELDS(getreg(base, MAS_SEC_0), PCIE_DOM, MAS_DOMAIN_1); SET32_BITFIELDS(getreg(base, MAS_DOM_1), SCP_SSPM_DOM, MAS_DOMAIN_2, CPU_EB_DOM, MAS_DOMAIN_2); + + /* + * Domain Remap: TINYSYS to non-EMI (3-bit to 4-bit) + * 1. SCP from 3 to 3 + * 2. others from XXX to 15 + */ + SET32_BITFIELDS(getreg(base, DOM_REMAP_0_0), + FOUR_BIT_DOM_REMAP_0, MAS_DOMAIN_15, + FOUR_BIT_DOM_REMAP_1, MAS_DOMAIN_15, + FOUR_BIT_DOM_REMAP_2, MAS_DOMAIN_15, + FOUR_BIT_DOM_REMAP_3, MAS_DOMAIN_3, + FOUR_BIT_DOM_REMAP_4, MAS_DOMAIN_15, + FOUR_BIT_DOM_REMAP_5, MAS_DOMAIN_15, + FOUR_BIT_DOM_REMAP_6, MAS_DOMAIN_15, + FOUR_BIT_DOM_REMAP_7, MAS_DOMAIN_15); + + /* + * Domain Remap: MMSYS slave domain remap (4-bit to 2-bit) + * 1. From domain 0 ~ 3 to domain 0 ~ 3 + * 2. others from XXX to domain 0 + */ + SET32_BITFIELDS(getreg(base, DOM_REMAP_0_0), + TWO_BIT_DOM_REMAP_0, MAS_DOMAIN_0, + TWO_BIT_DOM_REMAP_1, MAS_DOMAIN_1, + TWO_BIT_DOM_REMAP_2, MAS_DOMAIN_2, + TWO_BIT_DOM_REMAP_3, MAS_DOMAIN_3); + } static void peri_master_init(uintptr_t base) @@ -24,33 +51,50 @@ static void peri_master_init(uintptr_t base) SET32_BITFIELDS(getreg(base, MAS_DOM_0), SPM_DOM, MAS_DOMAIN_2); } -static uintptr_t devapc_base[DEVAPC_AO_MAX] = { - DEVAPC_INFRA_AO_BASE, - DEVAPC_PERI_AO_BASE, - DEVAPC_PERI2_AO_BASE, - DEVAPC_PERI_PAR_AO_BASE, - DEVAPC_FMEM_AO_BASE, -}; +static void fmem_master_init(uintptr_t base) +{ + /* Domain Remap: TINYSYS to EMI (3-bit to 4-bit) + * 1. SCP from 3 to 3 + * 2. others from XXX to 15 + */ + SET32_BITFIELDS(getreg(base, DOM_REMAP_0_0), + FOUR_BIT_DOM_REMAP_0, MAS_DOMAIN_15, + FOUR_BIT_DOM_REMAP_1, MAS_DOMAIN_15, + FOUR_BIT_DOM_REMAP_2, MAS_DOMAIN_15, + FOUR_BIT_DOM_REMAP_3, MAS_DOMAIN_3, + FOUR_BIT_DOM_REMAP_4, MAS_DOMAIN_15, + FOUR_BIT_DOM_REMAP_5, MAS_DOMAIN_15, + FOUR_BIT_DOM_REMAP_6, MAS_DOMAIN_15, + FOUR_BIT_DOM_REMAP_7, MAS_DOMAIN_15); +} -static void (*master_init[DEVAPC_AO_MAX])(uintptr_t) = { - infra_master_init, - peri_master_init, +struct devapc_init { + uintptr_t base; + void (*init)(uintptr_t base); +} devapc_init[DEVAPC_AO_MAX] = { + { DEVAPC_INFRA_AO_BASE, infra_master_init }, + { DEVAPC_PERI_AO_BASE, peri_master_init }, + { DEVAPC_PERI2_AO_BASE, NULL }, + { DEVAPC_PERI_PAR_AO_BASE, NULL }, + { DEVAPC_FMEM_AO_BASE, fmem_master_init }, }; void dapc_init(void) { int i; uintptr_t devapc_ao_base; + void (*init_func)(uintptr_t base); - for (i = 0; i < ARRAY_SIZE(devapc_base); i++) { - devapc_ao_base = devapc_base[i]; + for (i = 0; i < ARRAY_SIZE(devapc_init); i++) { + devapc_ao_base = devapc_init[i].base; + init_func = devapc_init[i].init; /* Init dapc */ write32(getreg(devapc_ao_base, AO_APC_CON), 0x0); write32(getreg(devapc_ao_base, AO_APC_CON), 0x1); /* Init master */ - if (master_init[i]) - master_init[i](devapc_ao_base); + if (init_func) + init_func(devapc_ao_base); } } diff --git a/src/soc/mediatek/mt8192/include/soc/devapc.h b/src/soc/mediatek/mt8192/include/soc/devapc.h index f227aaadd3d0..7ba6d46477a5 100644 --- a/src/soc/mediatek/mt8192/include/soc/devapc.h +++ b/src/soc/mediatek/mt8192/include/soc/devapc.h @@ -11,6 +11,10 @@ void dapc_init(void); #define DEVAPC_AO_MAX 6 enum devapc_ao_offset { + DOM_REMAP_0_0 = 0x800, + DOM_REMAP_1_0 = 0x810, + DOM_REMAP_1_1 = 0x814, + DOM_REMAP_2_0 = 0x820, MAS_DOM_0 = 0x0900, MAS_DOM_1 = 0x0904, MAS_SEC_0 = 0x0A00, @@ -48,5 +52,19 @@ enum master_domain { MAS_DOMAIN_MAX, }; +/* Domain Remap */ +DEFINE_BITFIELD(FOUR_BIT_DOM_REMAP_0, 3, 0) +DEFINE_BITFIELD(FOUR_BIT_DOM_REMAP_1, 7, 4) +DEFINE_BITFIELD(FOUR_BIT_DOM_REMAP_2, 11, 8) +DEFINE_BITFIELD(FOUR_BIT_DOM_REMAP_3, 15, 12) +DEFINE_BITFIELD(FOUR_BIT_DOM_REMAP_4, 19, 16) +DEFINE_BITFIELD(FOUR_BIT_DOM_REMAP_5, 23, 20) +DEFINE_BITFIELD(FOUR_BIT_DOM_REMAP_6, 27, 24) +DEFINE_BITFIELD(FOUR_BIT_DOM_REMAP_7, 31, 28) + +DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_0, 1, 0) +DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_1, 3, 2) +DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_2, 5, 4) +DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_3, 7, 6) #endif /* SOC_MEDIATEK_MT8192_DEVAPC_H */ |