diff options
| author | Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> | 2021-04-27 21:20:06 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-05-05 07:36:48 +0000 |
| commit | 47095d5ec35b4cbff9d4660cfe9521ed17a0d1ed (patch) | |
| tree | fe8a77a9c18fbadb256a274797c11cf554f7db18 /src/soc/mediatek/mt8192 | |
| parent | 0575778667e9802a3af9766f459f43f833330d88 (diff) | |
| download | coreboot-47095d5ec35b4cbff9d4660cfe9521ed17a0d1ed.tar.gz coreboot-47095d5ec35b4cbff9d4660cfe9521ed17a0d1ed.tar.bz2 coreboot-47095d5ec35b4cbff9d4660cfe9521ed17a0d1ed.zip | |
soc/mediatek: Move the common part of SPI drivers to common/
The SPI drivers can be shared by MT8183, MT8192 and MT8195.
TEST=emerge-{oak, kukui, asurada, cherry} coreboot;
verified on Cherry P0
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I7bb7809a88fbda67eca67ecfde45b9cb5f09dffe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8192')
| -rw-r--r-- | src/soc/mediatek/mt8192/include/soc/spi.h | 45 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8192/spi.c | 17 |
2 files changed, 12 insertions, 50 deletions
diff --git a/src/soc/mediatek/mt8192/include/soc/spi.h b/src/soc/mediatek/mt8192/include/soc/spi.h index 034fa3570ae7..db3ba216130f 100644 --- a/src/soc/mediatek/mt8192/include/soc/spi.h +++ b/src/soc/mediatek/mt8192/include/soc/spi.h @@ -7,38 +7,17 @@ #define SPI_BUS_NUMBER 8 -/* SPI peripheral register map. */ -typedef struct mtk_spi_regs { - uint32_t spi_cfg0_reg; - uint32_t spi_cfg1_reg; - uint32_t spi_tx_src_reg; - uint32_t spi_rx_dst_reg; - uint32_t spi_tx_data_reg; - uint32_t spi_rx_data_reg; - uint32_t spi_cmd_reg; - uint32_t spi_status0_reg; - uint32_t spi_status1_reg; - uint32_t spi_pad_macro_sel_reg; - uint32_t spi_cfg2_reg; - uint32_t spi_tx_src_64_reg; - uint32_t spi_rx_dst_64_reg; -} mtk_spi_regs; - -check_member(mtk_spi_regs, spi_pad_macro_sel_reg, 0x24); - -enum { - SPI_CFG0_CS_HOLD_SHIFT = 0, - SPI_CFG0_CS_SETUP_SHIFT = 16, -}; - -enum { - SPI_CFG2_SCK_LOW_SHIFT = 0, - SPI_CFG2_SCK_HIGH_SHIFT = 16, -}; - -enum { - SPI_CFG1_TICK_DLY_SHIFT = 29, - SPI_CFG1_TICK_DLY_MASK = 0x7 << SPI_CFG1_TICK_DLY_SHIFT, -}; +#define GET_SCK_REG(x) x->spi_cfg2_reg + +DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0) +DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16) + +DEFINE_BITFIELD(SPI_CFG_SCK_LOW, 15, 0) +DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 31, 16) + +DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0) +DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8) +DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 28, 16) +DEFINE_BITFIELD(SPI_CFG1_TICK_DLY, 31, 29) #endif diff --git a/src/soc/mediatek/mt8192/spi.c b/src/soc/mediatek/mt8192/spi.c index f7a8756d1a08..b5abc85b839b 100644 --- a/src/soc/mediatek/mt8192/spi.c +++ b/src/soc/mediatek/mt8192/spi.c @@ -112,23 +112,6 @@ void mtk_spi_set_gpio_pinmux(unsigned int bus, enum spi_pad_mask pad_select) gpio_set_mode((gpio_t){.id = ptr[i].pin_id}, ptr[i].func); } -void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks, - unsigned int tick_dly) -{ - write32(®s->spi_cfg0_reg, - ((cs_ticks - 1) << SPI_CFG0_CS_HOLD_SHIFT) | - ((cs_ticks - 1) << SPI_CFG0_CS_SETUP_SHIFT)); - - write32(®s->spi_cfg2_reg, - ((sck_ticks - 1) << SPI_CFG2_SCK_HIGH_SHIFT) | - ((sck_ticks - 1) << SPI_CFG2_SCK_LOW_SHIFT)); - - clrsetbits32(®s->spi_cfg1_reg, SPI_CFG1_TICK_DLY_MASK | - SPI_CFG1_CS_IDLE_MASK, - (tick_dly << SPI_CFG1_TICK_DLY_SHIFT) | - ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT)); -} - static const struct spi_ctrlr spi_flash_ctrlr = { .max_xfer_size = 65535, .flash_probe = mtk_spi_flash_probe, |