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| author | Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> | 2021-06-18 19:48:17 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-06-24 03:13:53 +0000 |
| commit | a9be096fa745e33bf880d2b3feec560384fd4573 (patch) | |
| tree | 5a97cdb218e73f964088dc8ddbdd7dbe9c6c88cf /src/soc/mediatek/mt8195/Kconfig | |
| parent | 6ce71e3bb1fe11b67f695c17456fc9295c784f39 (diff) | |
| download | coreboot-a9be096fa745e33bf880d2b3feec560384fd4573.tar.gz coreboot-a9be096fa745e33bf880d2b3feec560384fd4573.tar.bz2 coreboot-a9be096fa745e33bf880d2b3feec560384fd4573.zip | |
soc/mediatek/mt8195: Support 4 channel DRAM in DPM init flow
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: If2e9d8a4dcfad28c48a2b5fa7c92f70fae879e67
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8195/Kconfig')
| -rw-r--r-- | src/soc/mediatek/mt8195/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8195/Kconfig b/src/soc/mediatek/mt8195/Kconfig index 249d0877df1e..df1b5d8b4702 100644 --- a/src/soc/mediatek/mt8195/Kconfig +++ b/src/soc/mediatek/mt8195/Kconfig @@ -10,6 +10,7 @@ config SOC_MEDIATEK_MT8195 select HAVE_UART_SPECIAL select SOC_MEDIATEK_COMMON select CLEAR_WDT_MODE_REG + select DPM_FOUR_CHANNEL if SOC_MEDIATEK_MT8195 |