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| author | Tinghan Shen <tinghan.shen@mediatek.com> | 2022-03-31 15:56:01 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-05-25 12:52:29 +0000 |
| commit | fefd00043186d3b405f58be3daaa2312fdf3ef9e (patch) | |
| tree | d709f0e2df8f107da1211021123565c7539f4faf /src/soc/mediatek/mt8195/devapc.c | |
| parent | 453f841b2e9a0a0557771052e272f3f4f661f6bb (diff) | |
| download | coreboot-fefd00043186d3b405f58be3daaa2312fdf3ef9e.tar.gz coreboot-fefd00043186d3b405f58be3daaa2312fdf3ef9e.tar.bz2 coreboot-fefd00043186d3b405f58be3daaa2312fdf3ef9e.zip | |
soc/mediatek/mt8195: Configure SCP core 2 domain setting
SCP core 2 is enabled for MT8195 camera feature. It requires the same
register access permission as SCP core 1. Therefore, we configure the
same domain ID for both cores.
BRANCH=cherry
BUG=b:193814857
TEST=cherry boot ok
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Change-Id: Idf335593936b12c083c926a252fa99c3b76cda6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64575
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8195/devapc.c')
| -rw-r--r-- | src/soc/mediatek/mt8195/devapc.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/soc/mediatek/mt8195/devapc.c b/src/soc/mediatek/mt8195/devapc.c index ac3e6db8d613..2c41ff5d4ae9 100644 --- a/src/soc/mediatek/mt8195/devapc.c +++ b/src/soc/mediatek/mt8195/devapc.c @@ -1955,7 +1955,9 @@ static void infra2_init(uintptr_t base) static void scp_master_init(uintptr_t base) { - write32(getreg(base, SCP_DOM), DOMAIN_3); + SET32_BITFIELDS(getreg(base, SCP_DOM), + FOUR_BIT_DOM_REMAP_0, DOMAIN_3, + FOUR_BIT_DOM_REMAP_1, DOMAIN_3); write32(getreg(base, ADSP_DOM), DOMAIN_4); /* Let SCP_DOM and ADSP_DOM registers be read-only for security */ |