diff options
| author | Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> | 2021-12-21 12:52:40 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-12-26 10:05:22 +0000 |
| commit | f371a78d907666afde4d945a56f9ca1e9c2152c8 (patch) | |
| tree | 9dc7ab56424a3152f972cd0c208b90819e875c30 /src/soc/mediatek/mt8195/include/soc/dptx.h | |
| parent | d22cdbe73fb06e4fbb56884f83fcf27cca14e7e1 (diff) | |
| download | coreboot-f371a78d907666afde4d945a56f9ca1e9c2152c8.tar.gz coreboot-f371a78d907666afde4d945a56f9ca1e9c2152c8.tar.bz2 coreboot-f371a78d907666afde4d945a56f9ca1e9c2152c8.zip | |
soc/medaitek/mt8195: adjust USB phy shift value
There is a design issue of bit shift which will drop a bit for
USB3 phy on MT8195. Therefore, we add this patch to set USB phy
registers from value of efuse.
BUG=b:211528577
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Signed-off-by: Tianping Fang <tianping.fang@mediatek.corp-partner.google.com>
Tested-by: Tianping Fang <tianping.fang@mediatek.corp-partner.google.com>
Change-Id: I43cb6c1c795dd181d6eba7f3bc52e4eb1a602081
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60312
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8195/include/soc/dptx.h')
0 files changed, 0 insertions, 0 deletions