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| author | Rex-BC Chen <rex-bc.chen@mediatek.com> | 2022-07-25 19:52:14 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-08-03 16:40:20 +0000 |
| commit | 07c91d55db461b74320a2e04c035f2c5533a1622 (patch) | |
| tree | ca5963d2beb9b171a8f9ed3c25ccbdabccca14dd /src/soc/mediatek/mt8195/include/soc/dramc_soc.h | |
| parent | f9009dde545bc96840f381afc3170818a0d91e29 (diff) | |
| download | coreboot-07c91d55db461b74320a2e04c035f2c5533a1622.tar.gz coreboot-07c91d55db461b74320a2e04c035f2c5533a1622.tar.bz2 coreboot-07c91d55db461b74320a2e04c035f2c5533a1622.zip | |
mb/google/geralt: Implement SKU ID and RAM code
- Retrieve the SKU ID for Geralt via CBI interface. If that failed
(or no data found), fall back to ADC channels for SKU ID.
- The RAM code is implemented by the resistor straps that we can read
and decode from ADC.
TEST=build pass
BUG=b:236331724
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I31626e44bd873a3866c9bd1d511b476737f15a20
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66275
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8195/include/soc/dramc_soc.h')
0 files changed, 0 insertions, 0 deletions