soc/mediatek/mt8195: Initialize DRAM in romstage

Initialize DRAM in romstage and configure to support fast calibration.

Change-Id: I89b87be62c8e88ae4a620d56aa7a35e47f97952d
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54229
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 50 insertions, 0 deletions

diff --git a/src/soc/mediatek/mt8195/include/soc/dramc_soc.h b/src/soc/mediatek/mt8195/include/soc/dramc_soc.h
new file mode 100644
index 000000000000..60402979928c
--- /dev/null
+++ b/src/soc/mediatek/mt8195/include/soc/dramc_soc.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8195_DRAMC_SOC_H__
+#define __SOC_MEDIATEK_MT8195_DRAMC_SOC_H__
+
+typedef enum {
+	CHANNEL_A = 0,
+	CHANNEL_B,
+	CHANNEL_C,
+	CHANNEL_D,
+	CHANNEL_MAX,
+} DRAM_CHANNEL_T;
+
+typedef enum {
+	RANK_0 = 0,
+	RANK_1,
+	RANK_MAX,
+} DRAM_RANK_T;
+
+/* DRAM SHUFFLE register type */
+typedef enum {
+	DRAM_DFS_SHUFFLE_1 = 0,
+	DRAM_DFS_SHUFFLE_2,
+	DRAM_DFS_SHUFFLE_3,
+	DRAM_DFS_SHUFFLE_4,
+	DRAM_DFS_SHUFFLE_5,
+	DRAM_DFS_SHUFFLE_6,
+	DRAM_DFS_SHUFFLE_7,
+	DRAM_DFS_SHUFFLE_MAX,
+} DRAM_DFS_SHUFFLE_TYPE_T;
+
+/*
+ * Internal CBT mode enum
+ * 1. Calibration flow uses vGet_Dram_CBT_Mode to
+ *    differentiate between mixed vs non-mixed LP4
+ * 2. Declared as dram_cbt_mode[RANK_MAX] internally to
+ *    store each rank's CBT mode type
+ */
+typedef enum {
+	CBT_NORMAL_MODE = 0,
+	CBT_BYTE_MODE1,
+} DRAM_CBT_MODE_T;
+
+#define DRAM_DFS_SHU_MAX	DRAM_DFS_SHUFFLE_MAX
+
+#define DQS_NUMBER_LP4 2
+#define DQS_BIT_NUMBER 8
+#define DQ_DATA_WIDTH_LP4 16
+
+#endif	/* __SOC_MEDIATEK_MT8195_DRAMC_SOC_H__ */