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| author | Rex-BC Chen <rex-bc.chen@mediatek.com> | 2022-07-27 16:12:12 +0800 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-07-29 15:05:33 +0000 |
| commit | 00324b20e102f9f0f040077b584da12ba3fd699c (patch) | |
| tree | 4c170f7a84953dcdc98e5452c59c65ba420bc337 /src/soc/mediatek/mt8195/include | |
| parent | d699de071fee0572971170637fe3bd81dbc463c9 (diff) | |
| download | coreboot-00324b20e102f9f0f040077b584da12ba3fd699c.tar.gz coreboot-00324b20e102f9f0f040077b584da12ba3fd699c.tar.bz2 coreboot-00324b20e102f9f0f040077b584da12ba3fd699c.zip | |
soc/mediatek: Create GET_TICK_DLY_REG macro for SPI tick delay setting
MT8188 SPI tick delay setting is moved to `spi_cmd_reg` register which
is different from previous SoCs, so we define a macro to get the
designated register.
TEST=build pass.
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Ia30e94a8688c0e1c1d4b3d15206f28e5bd8c9bd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66184
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8195/include')
| -rw-r--r-- | src/soc/mediatek/mt8195/include/soc/spi.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/mediatek/mt8195/include/soc/spi.h b/src/soc/mediatek/mt8195/include/soc/spi.h index a74ed5643983..b51e503fd161 100644 --- a/src/soc/mediatek/mt8195/include/soc/spi.h +++ b/src/soc/mediatek/mt8195/include/soc/spi.h @@ -8,6 +8,7 @@ #define SPI_BUS_NUMBER 6 #define GET_SCK_REG(x) x->spi_cfg2_reg +#define GET_TICK_DLY_REG(x) x->spi_cfg1_reg DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0) DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16) @@ -18,6 +19,6 @@ DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 31, 16) DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0) DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8) DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 28, 16) -DEFINE_BITFIELD(SPI_CFG1_TICK_DLY, 31, 29) +DEFINE_BITFIELD(SPI_TICK_DLY, 31, 29) #endif |