soc/mediatek/mt8195: fix GPIO register offsets

Correct the offsets by MT8195 Register Map V0.2-1
chapter: 3.2 GPIO Controller (page 3272)

Control register names:
	PUPD_CFG0
	PU_CFG0

Signed-off-by: Zhiqiang Ma <zhiqiang.ma@mediatek.com>
Change-Id: I9b0f8a24756092a97933cc9d4ba13a9e79c73e91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55163
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 43 insertions, 43 deletions

diff --git a/src/soc/mediatek/mt8195/include/soc/gpio.h b/src/soc/mediatek/mt8195/include/soc/gpio.h
index 0739f634ae59..e5c1ff165b13 100644
--- a/src/soc/mediatek/mt8195/include/soc/gpio.h
+++ b/src/soc/mediatek/mt8195/include/soc/gpio.h
@@ -56,40 +56,40 @@ enum {
 	PIN(5, GPIO_05, 1, 5, 0x23, 0x60,
 	    TP_GPIO5_AO, MSDC2_DAT1, SPDIF_IN0, URXD3,
 	    SCL2, RES6, USB_DRVVBUS_2P),
-	PIN(6, GPIO_06, 0, 6, 0x23, 0x70,
+	PIN(6, GPIO_06, 0, 0, 0x23, 0x70,
 	    TP_GPIO6_AO, DP_TX_HPD, I2SO1_D4, UTXD4,
 	    CMVREF3, RES6, DMIC3_CLK),
-	PIN(7, GPIO_07, 0, 7, 0x23, 0x70,
+	PIN(7, GPIO_07, 0, 1, 0x23, 0x70,
 	    TP_GPIO7_AO, EDP_TX_HPD, I2SO1_D5, URXD4,
 	    CMVREF4, RES6, DMIC3_DAT),
-	PIN(8, SDA0, 0, 13, 0x23, 0x70,
+	PIN(8, SDA0, 0, 7, 0x23, 0x70,
 	    SDA0, PWM_0, RES3, SPDIF_OUT,
 	    RES5, LVTS_FOUT, DBG_MON_A0),
-	PIN(9, SCL0, 0, 8, 0x23, 0x70,
+	PIN(9, SCL0, 0, 2, 0x23, 0x70,
 	    SCL0, PWM_1, RES3, IR_IN,
 	    RES5, LVTS_SDO, DBG_MON_A1),
-	PIN(10, SDA1, 0, 14, 0x23, 0x70,
+	PIN(10, SDA1, 0, 8, 0x23, 0x70,
 	    SDA1, PWM_2, ADSP_URXD0, SPDIF_IN1,
 	    RES5, LVTS_SCF, DBG_MON_A2),
-	PIN(11, SCL1, 0, 9, 0x23, 0x70,
+	PIN(11, SCL1, 0, 3, 0x23, 0x70,
 	    SCL1, PWM_3, ADSP_UTXD0, SPDIF_IN0,
 	    RES5, LVTS_SCK, DBG_MON_A3),
-	PIN(12, SDA2, 0, 15, 0x23, 0x70,
+	PIN(12, SDA2, 0, 9, 0x23, 0x70,
 	    SDA2, DMIC3_DAT_R, I2SO1_D6, RES4,
 	    RES5, LVTS_SDI, DBG_MON_A4),
-	PIN(13, SCL2, 0, 10, 0x23, 0x70,
+	PIN(13, SCL2, 0, 4, 0x23, 0x70,
 	    SCL2, DMIC4_DAT_R, I2SO1_D7, RES4,
 	    RES5, RES6, DBG_MON_A5),
-	PIN(14, SDA3, 0, 16, 0x23, 0x70,
+	PIN(14, SDA3, 0, 10, 0x23, 0x70,
 	    SDA3, DMIC3_DAT, TDMIN_MCK, RES4,
 	    RES5, RES6, DBG_MON_A6),
-	PIN(15, SCL3, 0, 11, 0x23, 0x70,
+	PIN(15, SCL3, 0, 5, 0x23, 0x70,
 	    SCL3, DMIC3_CLK, TDMIN_DI, RES4,
 	    RES5, RES6, DBG_MON_A7),
-	PIN(16, SDA4, 0, 17, 0x23, 0x70,
+	PIN(16, SDA4, 0, 11, 0x23, 0x70,
 	    SDA4, DMIC4_DAT, TDMIN_LRCK, RES4,
 	    RES5, RES6, DBG_MON_A8),
-	PIN(17, SCL4, 0, 12, 0x23, 0x70,
+	PIN(17, SCL4, 0, 6, 0x23, 0x70,
 	    SCL4, DMIC4_CLK, TDMIN_BCK, RES4,
 	    RES5, RES6, DBG_MON_A9),
 	PIN(18, DPTX_HPD, 0, 5, 0x10, 0x60,
@@ -170,10 +170,10 @@ enum {
 	PIN(43, PWRAP_SPI_MI, 0, 9, 0x21, 0xb0,
 	    PWRAP_SPI0_MI, PWRAP_SPI0_MO, SPIM3_MI, RES4,
 	    RES5, RES6, DBG_MON_B1),
-	PIN(44, SPMI_M_SCL, 0, 20, 0x21, 0xb0,
+	PIN(44, SPMI_M_SCL, 0, 21, 0x21, 0xb0,
 	    SPMI_M_SCL, I2SI00_DATA1, SCL5, UTXD5,
 	    RES5, RES6, DBG_MON_B2),
-	PIN(45, SPMI_M_SDA, 0, 21, 0x21, 0xb0,
+	PIN(45, SPMI_M_SDA, 0, 22, 0x21, 0xb0,
 	    SPMI_M_SDA, I2SI00_DATA2, SDA5, URXD5,
 	    RES5, RES6, DBG_MON_B3),
 	PIN(46, I2SIN_MCK, 0, 18, 0x21, 0xa0,
@@ -329,43 +329,43 @@ enum {
 	PIN(96, DGI_CK, 1, 0, 0x22, 0x60,
 	    DGI_CK, DPI_CK, URXD2, I2SO5_MCK,
 	    I2SIN_D2, CCU0_JTAG_TRST, RES7),
-	PIN(97, DISP_PWM0, 0, 20, 0x22, 0x70,
+	PIN(97, DISP_PWM0, 0, 0, 0x22, 0x70,
 	    DISP_PWM0, DVFSRC_EXT_REQ, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(98, UART0_TXD, 0, 28, 0x22, 0x70,
+	PIN(98, UART0_TXD, 0, 4, 0x22, 0x70,
 	    UTXD0, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(99, UART0_RXD, 0, 27, 0x22, 0x70,
+	PIN(99, UART0_RXD, 0, 3, 0x22, 0x70,
 	    URXD0, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(100, UART1_RTS, 0, 30, 0x22, 0x70,
+	PIN(100, UART1_RTS, 0, 6, 0x22, 0x70,
 	    URTS1, DSI_TE, I2SO1_D8, KPROW2,
 	    PWM_0, TP_URTS1_AO, I2SIN_D0),
-	PIN(101, UART1_CTS, 0, 29, 0x22, 0x70,
+	PIN(101, UART1_CTS, 0, 5, 0x22, 0x70,
 	    UCTS1, DSI1_TE, I2SO1_D9, KPCOL2,
 	    PWM_1, TP_UCTS1_AO, I2SIN_D1),
-	PIN(102, UART1_TXD, 0, 0, 0x22, 0x70,
+	PIN(102, UART1_TXD, 0, 8, 0x22, 0x70,
 	    UTXD1, VBUSVALID_2P, I2SO1_D10, SSPM_UTXD_AO,
 	    TP_UTXD1_AO, MD32_1_TXD, I2SIN_D2),
-	PIN(103, UART1_RXD, 0, 31, 0x22, 0x70,
+	PIN(103, UART1_RXD, 0, 7, 0x22, 0x70,
 	    URXD1, VBUSVALID_3P, I2SO1_D11, SSPM_URXD_AO,
 	    TP_URXD1_AO, MD32_1_RXD, I2SIN_D3),
-	PIN(104, KPROW0, 1, 25, 0x22, 0x60,
+	PIN(104, KPROW0, 1, 22, 0x22, 0x60,
 	    KPROW0, DISP_PWM1, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(105, KPROW1, 1, 26, 0x22, 0x60,
+	PIN(105, KPROW1, 1, 23, 0x22, 0x60,
 	    KPROW1, EDP_TX_HPD, PWM_2, RES4,
 	    RES5, RES6, RES7),
-	PIN(106, KPCOL0, 1, 23, 0x22, 0x60,
+	PIN(106, KPCOL0, 1, 20, 0x22, 0x60,
 	    KPCOL0, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(107, KPCOL1, 1, 24, 0x22, 0x60,
+	PIN(107, KPCOL1, 1, 21, 0x22, 0x60,
 	    KPCOL1, DSI1_TE, PWM_3, SCP_SCL3,
 	    I2SIN_MCK, RES6, RES7),
-	PIN(108, DSI_LCM_RST, 0, 22, 0x22, 0x70,
+	PIN(108, DSI_LCM_RST, 0, 2, 0x22, 0x70,
 	    LCM_RST, KPCOL1, RES3, SCP_SDA3,
 	    I2SIN_BCK, RES6, RES7),
-	PIN(109, DSI_DSI_TE, 0, 21, 0x22, 0x70,
+	PIN(109, DSI_DSI_TE, 0, 1, 0x22, 0x70,
 	    DSI_TE, I2SIN_D3, RES3, RES4,
 	    I2SIN_WS, RES6, RES7),
 	PIN(110, MSDC1_CMD, 1, 1, 0x14, 0x20,
@@ -421,52 +421,52 @@ enum {
 	PIN(127, EMMC_DSL, 1, 10, 0x25, 0x50,
 	    MSDC0_DSL, RES2, RES3, RES4,
 	    RES5, RES6, RES7),
-	PIN(128, USB_IDDIG, 0, 3, 0x22, 0x70,
+	PIN(128, USB_IDDIG, 0, 11, 0x22, 0x70,
 	    IDDIG, UCTS2, UTXD5, UFS_MPHY_SCL,
 	    mbistreaden_trigger, MD32_1_GPIO0, SCP_SCL2),
-	PIN(129, USB_DRV_VBUS, 0, 1, 0x22, 0x70,
+	PIN(129, USB_DRV_VBUS, 0, 9, 0x22, 0x70,
 	    SB_DRVVBUS, URTS2, URXD5, UFS_MPHY_SDA,
 	    mbistwriteen_trigger, MD32_1_GPIO1, SCP_SDA2),
-	PIN(130, USB_IDDIG_1P, 0, 4, 0x22, 0x70,
+	PIN(130, USB_IDDIG_1P, 0, 12, 0x22, 0x70,
 	    IDDIG_1P, SPINOR_IO2, SNFI_WP, VPU_UDI_NTRST,
 	    RES5, RES6, RES7),
-	PIN(131, USB_DRV_VBUS_1P, 0, 2, 0x22, 0x70,
+	PIN(131, USB_DRV_VBUS_1P, 0, 10, 0x22, 0x70,
 	    USB_DRVVBUS_1P, SPINOR_IO3, SNFI_HOLD, MD32_1_JTAG_TRST,
 	    SCP_JTAG0_TRSTN, APU_JTAG_TRST, RES7),
-	PIN(132, SPIM0_CSB, 0, 13, 0x25, 0x60,
+	PIN(132, SPIM0_CSB, 0, 1, 0x25, 0x60,
 	    SPIM0_CSB, SCP_SPI0_CS, SPIS0_CSB, VPU_UDI_TMS,
 	    RES5, I2SO5_D0, RES7),
-	PIN(133, SPIM0_CLK, 0, 12, 0x25, 0x60,
+	PIN(133, SPIM0_CLK, 0, 0, 0x25, 0x60,
 	    SPIM0_CLK, SCP_SPI0_CK, SPIS0_CLK, VPU_UDI_TCK,
 	    RES5, I2SO5_BCK, RES7),
-	PIN(134, SPIM0_MO, 0, 15, 0x25, 0x60,
+	PIN(134, SPIM0_MO, 0, 3, 0x25, 0x60,
 	    SPIM0_MO, SCP_SPI0_MO, SPIS0_SI, VPU_UDI_TDO,
 	    RES5, I2SO5_WS, RES7),
-	PIN(135, SPIM0_MI, 0, 14, 0x25, 0x60,
+	PIN(135, SPIM0_MI, 0, 2, 0x25, 0x60,
 	    SPIM0_MI, SCP_SPI0_MI, SPIS0_SO, VPU_UDI_TDI,
 	    RES5, I2SO5_MCK, RES7),
-	PIN(136, SPIM1_CSB, 0, 13, 0x21, 0xb0,
+	PIN(136, SPIM1_CSB, 0, 14, 0x21, 0xb0,
 	    SPIM1_CSB, SCP_SPI1_A_CS, SPIS1_CSB, MD32_1_JTAG_TMS,
 	    SCP_JTAG0_TMS, APU_JTAG_TMS, DBG_MON_A15),
-	PIN(137, SPIM1_CLK, 0, 12, 0x21, 0xb0,
+	PIN(137, SPIM1_CLK, 0, 13, 0x21, 0xb0,
 	    SPIM1_CLK, SCP_SPI1_A_CK, SPIS1_CLK, MD32_1_JTAG_TCK,
 	    SCP_JTAG0_TCK, APU_JTAG_TCK, DBG_MON_A14),
-	PIN(138, SPIM1_MO, 0, 15, 0x21, 0xb0,
+	PIN(138, SPIM1_MO, 0, 16, 0x21, 0xb0,
 	    SPIM1_MO, SCP_SPI1_A_MO, SPIS1_SI, MD32_1_JTAG_TDO,
 	    SCP_JTAG0_TDO, APU_JTAG_TDO, DBG_MON_A16),
-	PIN(139, SPIM1_MI, 0, 14, 0x21, 0xb0,
+	PIN(139, SPIM1_MI, 0, 15, 0x21, 0xb0,
 	    SPIM1_MI, SCP_SPI1_A_MI, SPIS1_SO, MD32_1_JTAG_TDI,
 	    SCP_JTAG0_TDI, APU_JTAG_TDI, DBG_MON_A17),
-	PIN(140, SPIM2_CSB, 0, 17, 0x21, 0xb0,
+	PIN(140, SPIM2_CSB, 0, 18, 0x21, 0xb0,
 	    SPIM2_CSB, SPINOR_CS, SNFI_CS, DMIC3_DAT,
 	    RES5, RES6, DBG_MON_A11),
-	PIN(141, SPIM2_CLK, 0, 16, 0x21, 0xb0,
+	PIN(141, SPIM2_CLK, 0, 17, 0x21, 0xb0,
 	    SPIM2_CLK, SPINOR_CK, SNFI_CLK, DMIC3_CLK,
 	    RES5, RES6, DBG_MON_A10),
-	PIN(142, SPIM2_MO, 0, 19, 0x21, 0xb0,
+	PIN(142, SPIM2_MO, 0, 20, 0x21, 0xb0,
 	    SPIM2_MO, SPINOR_IO0, SNFI_MOSI, DMIC4_DAT,
 	    RES5, RES6, DBG_MON_A12),
-	PIN(143, SPIM2_MI, 0, 18, 0x21, 0xb0,
+	PIN(143, SPIM2_MI, 0, 19, 0x21, 0xb0,
 	    PIM2_MI, SPINOR_IO1, SNFI_MISO, DMIC4_CLK,
 	    RES5, RES6, DBG_MON_A13),
 };