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| author | Yidi Lin <yidi.lin@mediatek.com> | 2021-04-19 16:06:55 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-05-11 03:54:09 +0000 |
| commit | be8621d7854d28cc4ac1a2c07e8de6ddfb9d5a0c (patch) | |
| tree | 643cd286d0b14f6f54f2ad43d9457e7910c43f7f /src/soc/mediatek/mt8195/include | |
| parent | 9a056013411a79ca7973c6a141d78e22949d4553 (diff) | |
| download | coreboot-be8621d7854d28cc4ac1a2c07e8de6ddfb9d5a0c.tar.gz coreboot-be8621d7854d28cc4ac1a2c07e8de6ddfb9d5a0c.tar.bz2 coreboot-be8621d7854d28cc4ac1a2c07e8de6ddfb9d5a0c.zip | |
soc/mediatek/mt8195: Disable UFS reference clock
UFS reference clock (refclk) is enabled by default, which will cause
the UFSHCI to hold the SPM signal and lead to suspend failure. Since
UFS kernel driver is not built-in, disable refclk in coreboot stage.
Change UFSHCI base register to 0x11270000.
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: I1386e59f802a9e3c938a7e8dbeea547fbcb02709
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8195/include')
| -rw-r--r-- | src/soc/mediatek/mt8195/include/soc/addressmap.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/mediatek/mt8195/include/soc/addressmap.h b/src/soc/mediatek/mt8195/include/soc/addressmap.h index db24b7706a9c..60b730a391be 100644 --- a/src/soc/mediatek/mt8195/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8195/include/soc/addressmap.h @@ -61,6 +61,7 @@ enum { SPIS1_BASE = IO_PHYS + 0x0101E000, SSUSB_IPPC_BASE = IO_PHYS + 0x01203E00, MSDC0_BASE = IO_PHYS + 0x01230000, + UFSHCI_BASE = IO_PHYS + 0x01270000, SFLASH_REG_BASE = IO_PHYS + 0x0132C000, EFUSEC_BASE = IO_PHYS + 0x01C10000, MIPITX_BASE = IO_PHYS + 0x01C80000, @@ -73,7 +74,6 @@ enum { IOCFG_RB_BASE = IO_PHYS + 0x01EB0000, IOCFG_TL_BASE = IO_PHYS + 0x01F40000, MSDC0_TOP_BASE = IO_PHYS + 0x01F50000, - UFSHCI_BASE = IO_PHYS + 0x01FA0000, DISP_OVL0_BASE = IO_PHYS + 0x0C000000, DISP_RDMA0_BASE = IO_PHYS + 0x0C002000, DISP_COLOR0_BASE = IO_PHYS + 0x0C003000, |