diff options
| author | Weiyi Lu <weiyi.lu@mediatek.com> | 2021-02-09 17:59:26 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-05-05 07:38:06 +0000 |
| commit | 16bc621262f30fb024f37a45a8c1bb418b02b9a5 (patch) | |
| tree | ad8df737691bf3198d722df1f22c2a180fc3f205 /src/soc/mediatek/mt8195/mtcmos.c | |
| parent | 7fd932744e68fed23944012ac3d9e7c193402f8b (diff) | |
| download | coreboot-16bc621262f30fb024f37a45a8c1bb418b02b9a5.tar.gz coreboot-16bc621262f30fb024f37a45a8c1bb418b02b9a5.tar.bz2 coreboot-16bc621262f30fb024f37a45a8c1bb418b02b9a5.zip | |
soc/mediatek/mt8195: Add mtcmos init support
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: If7cd1f596f1406fa21d6586510e9956bb9846a6f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8195/mtcmos.c')
| -rw-r--r-- | src/soc/mediatek/mt8195/mtcmos.c | 77 |
1 files changed, 77 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8195/mtcmos.c b/src/soc/mediatek/mt8195/mtcmos.c new file mode 100644 index 000000000000..e19444186870 --- /dev/null +++ b/src/soc/mediatek/mt8195/mtcmos.c @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <soc/infracfg.h> +#include <soc/mtcmos.h> + +enum { + VPPSYS0_PROT_STEP_6_MASK = 0x00100000, + VPPSYS0_PROT_STEP_5_MASK = 0x0007F8FF, + VPPSYS0_PROT_STEP_4_MASK = 0x00800000, + VPPSYS0_PROT_STEP_3_MASK = 0x01600300, + VPPSYS0_PROT_STEP_2_MASK = 0x80381DC7, + VPPSYS0_PROT_STEP_1_MASK = 0x00000400, + + VDOSYS0_PROT_STEP_5_MASK = 0x00200000, + VDOSYS0_PROT_STEP_4_MASK = 0x3FC00000, + VDOSYS0_PROT_STEP_3_MASK = 0x00000040, + VDOSYS0_PROT_STEP_2_MASK = 0x00800000, + VDOSYS0_PROT_STEP_1_MASK = 0x403E6238, + + VPPSYS1_PROT_STEP_3_MASK = 0x000400C0, + VPPSYS1_PROT_STEP_2_MASK = 0x00800000, + VPPSYS1_PROT_STEP_1_MASK = 0x000001E0, + + VDOSYS1_PROT_STEP_3_MASK = 0x00000400, + VDOSYS1_PROT_STEP_2_MASK = 0x00400000, + VDOSYS1_PROT_STEP_1_MASK = 0xC0000000, + + AUDIO_PROT_STEP_1_MASK = 0x00000600, +}; + +void mtcmos_protect_display_bus(void) +{ + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_sub_infra_vdnr_clr, + VPPSYS0_PROT_STEP_6_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr_2, + VPPSYS0_PROT_STEP_5_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_clr, + VPPSYS0_PROT_STEP_4_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr_2, + VPPSYS0_PROT_STEP_3_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr, + VPPSYS0_PROT_STEP_2_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_clr, + VPPSYS0_PROT_STEP_1_MASK); + + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_sub_infra_vdnr_clr, + VDOSYS0_PROT_STEP_5_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr, + VDOSYS0_PROT_STEP_4_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_clr, + VDOSYS0_PROT_STEP_3_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr_2, + VDOSYS0_PROT_STEP_2_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr, + VDOSYS0_PROT_STEP_1_MASK); + + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr_2, + VPPSYS1_PROT_STEP_3_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr, + VPPSYS1_PROT_STEP_2_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr, + VPPSYS1_PROT_STEP_1_MASK); + + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr_2, + VDOSYS1_PROT_STEP_3_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr, + VDOSYS1_PROT_STEP_2_MASK); + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr, + VDOSYS1_PROT_STEP_1_MASK); +} + +void mtcmos_protect_audio_bus(void) +{ + write32(&mt8195_infracfg_ao->infra_topaxi_protecten_clr_2, + AUDIO_PROT_STEP_1_MASK); +} |