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| author | Jianjun Wang <jianjun.wang@mediatek.com> | 2022-03-23 15:38:56 +0800 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-03-29 15:41:50 +0000 |
| commit | aa751cc371699be04e656f20af9081bd092669bb (patch) | |
| tree | efbede7d3cdca01ef63870d8c82b762e65ee8510 /src/soc/mediatek/mt8195/pcie.c | |
| parent | 2183484e7aefdd576d01342ba4a7db74b480e8a3 (diff) | |
| download | coreboot-aa751cc371699be04e656f20af9081bd092669bb.tar.gz coreboot-aa751cc371699be04e656f20af9081bd092669bb.tar.bz2 coreboot-aa751cc371699be04e656f20af9081bd092669bb.zip | |
soc/mediatek: Ensure PERST# deassertion time follows the spec
According to the PCIe CEM specification, the deassertion of PERST#
should occur at least 100ms after the assertion. To ensure the 100ms
delay requirement is met, calculate the elapsed time since assertion. If
it is smaller than 100ms, do an extra delay.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the measured PERST# time:
[DEBUG] mtk_pcie_domain_enable: 432517 us elapsed since assert PERST#
[INFO ] mtk_pcie_domain_enable: PCIe link up success (17 tries)
And the SSD information in boot log is as follows:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
BRANCH=cherry
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ie2b7b6174abdf951af5796ab5ed141c45f32fc71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8195/pcie.c')
| -rw-r--r-- | src/soc/mediatek/mt8195/pcie.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8195/pcie.c b/src/soc/mediatek/mt8195/pcie.c index 1a17c6c459a2..df347c076823 100644 --- a/src/soc/mediatek/mt8195/pcie.c +++ b/src/soc/mediatek/mt8195/pcie.c @@ -6,6 +6,7 @@ #include <device/resource.h> #include <delay.h> #include <soc/addressmap.h> +#include <soc/early_init.h> #include <soc/gpio.h> #include <soc/pcie.h> #include <soc/pcie_common.h> @@ -72,4 +73,6 @@ void mtk_pcie_pre_init(void) /* Assert all reset signals at early stage */ mtk_pcie_reset(PCIE_RST_CTRL_REG, true); + + early_init_save_time(EARLY_INIT_PCIE); } |