diff options
| author | Jianjun Wang <jianjun.wang@mediatek.com> | 2022-03-14 20:38:18 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-03-16 16:55:26 +0000 |
| commit | c0808b64978056e72514525733e290b495cc0777 (patch) | |
| tree | 6e2b3524085e84450e445adb108d1f6aa03d484c /src/soc/mediatek/mt8195/pcie.c | |
| parent | d59b3dd08540b7cf42dc98d68da42b2a4305f6ee (diff) | |
| download | coreboot-c0808b64978056e72514525733e290b495cc0777.tar.gz coreboot-c0808b64978056e72514525733e290b495cc0777.tar.bz2 coreboot-c0808b64978056e72514525733e290b495cc0777.zip | |
soc/mediatek: Add chip config for setting PCIe config
Add chip config for setting PCIe config.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Icff83f2a9f76862065987a74cfcc7e511be80a20
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8195/pcie.c')
| -rw-r--r-- | src/soc/mediatek/mt8195/pcie.c | 27 |
1 files changed, 1 insertions, 26 deletions
diff --git a/src/soc/mediatek/mt8195/pcie.c b/src/soc/mediatek/mt8195/pcie.c index 8a1fca479b79..1a17c6c459a2 100644 --- a/src/soc/mediatek/mt8195/pcie.c +++ b/src/soc/mediatek/mt8195/pcie.c @@ -19,23 +19,6 @@ #define PCIE_BRG_RSTB BIT(2) #define PCIE_PE_RSTB BIT(3) - -/* MMIO range (64MB): 0x20000000 ~ 0x24000000 */ -/* Some devices still need io ranges, reserve 16MB for compatibility */ -static const struct mtk_pcie_mmio_res pcie_mmio_res_io = { - .cpu_addr = 0x20000000, - .pci_addr = 0x20000000, - .size = 16 * MiB, - .type = IORESOURCE_IO, -}; - -static const struct mtk_pcie_mmio_res pcie_mmio_res_mem = { - .cpu_addr = 0x21000000, - .pci_addr = 0x21000000, - .size = 48 * MiB, - .type = IORESOURCE_MEM, -}; - struct pad_func { gpio_t gpio; u8 func; @@ -67,7 +50,7 @@ static void mtk_pcie_set_pinmux(uint8_t port) } } -static void mtk_pcie_reset(uintptr_t reg, bool enable) +void mtk_pcie_reset(uintptr_t reg, bool enable) { uint32_t val; @@ -90,11 +73,3 @@ void mtk_pcie_pre_init(void) /* Assert all reset signals at early stage */ mtk_pcie_reset(PCIE_RST_CTRL_REG, true); } - -void mtk_pcie_get_hw_info(struct mtk_pcie_controller *ctrl) -{ - ctrl->base = PCIE_REG_BASE_PORT0; - ctrl->mmio_res_io = &pcie_mmio_res_io; - ctrl->mmio_res_mem = &pcie_mmio_res_mem; - ctrl->reset = &mtk_pcie_reset; -} |