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| author | Rex-BC Chen <rex-bc.chen@mediatek.com> | 2021-05-03 16:25:49 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-05-05 07:36:26 +0000 |
| commit | 3d6816abcdc2a72d1553d5e94c7e5a9eed13feae (patch) | |
| tree | 2d16a70e9d65b4294949a98416744fd6ca0f1add /src/soc/mediatek/mt8195/pmif_spi.c | |
| parent | bce4f2f70f5422e1d16d2d9efb4a29e484127b17 (diff) | |
| download | coreboot-3d6816abcdc2a72d1553d5e94c7e5a9eed13feae.tar.gz coreboot-3d6816abcdc2a72d1553d5e94c7e5a9eed13feae.tar.bz2 coreboot-3d6816abcdc2a72d1553d5e94c7e5a9eed13feae.zip | |
soc/mediatek/mt8195: add pmif/spmi/pmic driver
MT8195 also uses mt6359p so we can reuse most drivers.
The only differences are IO configuaration, clock setting, and PMIC
internal setting related to soc.
Reference datasheet: MT6315 datasheet v1.4.2.pdf, RH-D-2019-0616.
Reference datasheet: MT6359_PMIC_Data_Sheet_V1.5.docx, RH-D-2018-0205.
Change-Id: I73f9c9bf92837f262c15758f16dacf52261dd3a3
Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8195/pmif_spi.c')
| -rw-r--r-- | src/soc/mediatek/mt8195/pmif_spi.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8195/pmif_spi.c b/src/soc/mediatek/mt8195/pmif_spi.c new file mode 100644 index 000000000000..ddb217551696 --- /dev/null +++ b/src/soc/mediatek/mt8195/pmif_spi.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <soc/iocfg.h> +#include <soc/pmif_spi.h> + +/* IOCFG_BM, PWRAP_SPI0_DRIVING */ +DEFINE_BITFIELD(PWRAP_SPI0_DRIVING, 29, 24) +DEFINE_BITFIELD(PWRAP_SPI1_DRIVING, 5, 0) + +void pmif_spi_iocfg(void) +{ + /* Set SoC SPI IO driving strength to 4 mA */ + SET32_BITFIELDS(&mtk_iocfg_bm->drv_cfg1, PWRAP_SPI0_DRIVING, IO_4_MA); + SET32_BITFIELDS(&mtk_iocfg_bm->drv_cfg2, PWRAP_SPI1_DRIVING, IO_4_MA); +} |