summaryrefslogtreecommitdiffstats
path: root/src/soc/mediatek/mt8195/soc.c
diff options
context:
space:
mode:
authorYidi Lin <yidi.lin@mediatek.com>2021-01-07 20:25:54 +0800
committerHung-Te Lin <hungte@chromium.org>2021-04-13 06:07:54 +0000
commit24ea3f3364711f352a8a174e6fc0f22885725ed5 (patch)
tree4f055221846c974ec16c5d4aa7f7838cfe1ce55e /src/soc/mediatek/mt8195/soc.c
parent2bb361f0f5151f0cbf0bfcde085c05ca38c42de9 (diff)
downloadcoreboot-24ea3f3364711f352a8a174e6fc0f22885725ed5.tar.gz
coreboot-24ea3f3364711f352a8a174e6fc0f22885725ed5.tar.bz2
coreboot-24ea3f3364711f352a8a174e6fc0f22885725ed5.zip
soc/mediatek/mt8195: Add a stub implementation of the MT8195 SoC
TEST=boot from SPI-NOR and show console message at bootblock stage. Change-Id: Ia93430006096b7410393ab31fee4ea40598d0b34 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8195/soc.c')
-rw-r--r--src/soc/mediatek/mt8195/soc.c29
1 files changed, 29 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8195/soc.c b/src/soc/mediatek/mt8195/soc.c
new file mode 100644
index 000000000000..af28dd439778
--- /dev/null
+++ b/src/soc/mediatek/mt8195/soc.c
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <soc/emi.h>
+#include <symbols.h>
+
+static void soc_read_resources(struct device *dev)
+{
+ ram_resource(dev, 0, (uintptr_t)_dram / KiB, sdram_size() / KiB);
+}
+
+static void soc_init(struct device *dev)
+{
+}
+
+static struct device_operations soc_ops = {
+ .read_resources = soc_read_resources,
+ .init = soc_init,
+};
+
+static void enable_soc_dev(struct device *dev)
+{
+ dev->ops = &soc_ops;
+}
+
+struct chip_operations soc_mediatek_mt8195_ops = {
+ CHIP_NAME("SOC Mediatek MT8195")
+ .enable_dev = enable_soc_dev,
+};