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| author | Yidi Lin <yidi.lin@mediatek.com> | 2021-03-25 17:50:14 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-05-07 10:20:30 +0000 |
| commit | 27be90424b7cb8fd51c7ff6b6812601b9d091b6b (patch) | |
| tree | 16cd31cd458da50046de687605d251e5b912e724 /src/soc/mediatek/mt8195/soc.c | |
| parent | a21797a51ed06dc9a5bff81a9e50c177e7ac23fa (diff) | |
| download | coreboot-27be90424b7cb8fd51c7ff6b6812601b9d091b6b.tar.gz coreboot-27be90424b7cb8fd51c7ff6b6812601b9d091b6b.tar.bz2 coreboot-27be90424b7cb8fd51c7ff6b6812601b9d091b6b.zip | |
soc/mediatek/mt8195: Turn off L2C SRAM and reconfigure as L2 cache
Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready.
After DRAM is ready, we should invoke disable_l2c_sram to reconfigure
the L2C SRAM as L2 cache.
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: I8777b0c8471fe17ffffdcb6ad5b7c00fb1d35db1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52925
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8195/soc.c')
| -rw-r--r-- | src/soc/mediatek/mt8195/soc.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8195/soc.c b/src/soc/mediatek/mt8195/soc.c index af28dd439778..4c98a662f920 100644 --- a/src/soc/mediatek/mt8195/soc.c +++ b/src/soc/mediatek/mt8195/soc.c @@ -2,6 +2,7 @@ #include <device/device.h> #include <soc/emi.h> +#include <soc/mmu_operations.h> #include <symbols.h> static void soc_read_resources(struct device *dev) @@ -11,6 +12,7 @@ static void soc_read_resources(struct device *dev) static void soc_init(struct device *dev) { + mtk_mmu_disable_l2c_sram(); } static struct device_operations soc_ops = { |