soc/mediatek: Unify PLL function names

For consistency with the PLL function naming:
- Rename edp_mux_set_sel() to mt_pll_edp_mux_set_sel().
- Rename mux_set_sel() to pll_mux_set_sel().

BUG=none
TEST=build pass.
BRANCH=corsola

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Ifc7b14bf0db5a5461037e2fbf41756d1542ca945
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68622
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 4 insertions, 4 deletions

diff --git a/src/soc/mediatek/mt8195/dp_intf.c b/src/soc/mediatek/mt8195/dp_intf.c
index 69a7740392fc..ab2070ee0f4a 100644
--- a/src/soc/mediatek/mt8195/dp_intf.c
+++ b/src/soc/mediatek/mt8195/dp_intf.c
@@ -221,7 +221,7 @@ static int mtk_dpintf_power_on(struct mtk_dpintf *dpintf, const struct edid *edi
 	pll_rate = edid->mode.pixel_clock * 1000 * (1 << ((clksrc + 1) / 2));
 
 	mt_pll_set_tvd_pll1_freq(pll_rate / 4);
-	edp_mux_set_sel(clksrc);
+	mt_pll_edp_mux_set_sel(clksrc);
 
 	mtk_dpintf_enable(dpintf);
 
diff --git a/src/soc/mediatek/mt8195/pll.c b/src/soc/mediatek/mt8195/pll.c
index 06b2156702b5..792af7f360ba 100644
--- a/src/soc/mediatek/mt8195/pll.c
+++ b/src/soc/mediatek/mt8195/pll.c
@@ -755,7 +755,7 @@ void mt_pll_init(void)
 	 * TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS!
 	 */
 	for (i = 0; i < ARRAY_SIZE(mux_sels); i++)
-		mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);
+		pll_mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);
 
 	/* switch sram control to bypass mode for PCIE_MAC_P0 */
 	setbits32(&mtk_spm->ap_mdsrc_req, 0x1);
@@ -827,9 +827,9 @@ void mt_pll_set_tvd_pll1_freq(u32 freq)
 	udelay(PLL_EN_DELAY);
 }
 
-void edp_mux_set_sel(u32 sel)
+void mt_pll_edp_mux_set_sel(u32 sel)
 {
-	mux_set_sel(&muxes[TOP_EDP_SEL], sel);
+	pll_mux_set_sel(&muxes[TOP_EDP_SEL], sel);
 }
 
 u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id)