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| author | Huayang Duan <huayang.duan@mediatek.com> | 2020-03-18 13:49:00 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-18 16:47:06 +0000 |
| commit | 31b081a48d1cd654624c17b32265bd1e079e3912 (patch) | |
| tree | 4f493bc33fe263b0dd53576c50c2734cea8acd68 /src/soc/mediatek | |
| parent | c4917775fd310b93681c172d2e6b5a871b3dd36d (diff) | |
| download | coreboot-31b081a48d1cd654624c17b32265bd1e079e3912.tar.gz coreboot-31b081a48d1cd654624c17b32265bd1e079e3912.tar.bz2 coreboot-31b081a48d1cd654624c17b32265bd1e079e3912.zip | |
soc/mediatek/mt8183: Fix wrong setting of DRS config
Update setting of DRS config.
BUG=none
BRANCH=kukui
TEST=Boots correctly on Kukui
Change-Id: Id38fc224b54c3947af8bbc5c1a4a8d70eb53d5fb
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/soc/mediatek')
| -rw-r--r-- | src/soc/mediatek/mt8183/dramc_pi_basic_api.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index 0ee4794d4307..850f2b2ba1ea 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -485,9 +485,10 @@ void dramc_runtime_config(void) /* DRAM DRS DISABLE */ clrsetbits32(&ch[chn].ao.drsctrl, - (0x1 << 21) | (0x3f << 12) | (0xf << 8) | (0x1 << 6), - (0x1 << 19) | (0x3 << 12) | (0x8 << 8) | - (0x3 << 4) | (0x1 << 2) | (0x1 << 0)); + (0x1 << 0) | (0x1 << 2) | (0x1 << 4) | (0x1 << 5) | (0x1 << 6) | + (0xf << 8) | (0x7f << 12) | (0x1 << 19) | (0x1 << 21), + (0x1 << 0) | (0x0 << 2) | (0x0 << 4) | (0x1 << 5) | (0x0 << 6) | + (0x8 << 8) | (0x3 << 12) | (0x1 << 19) | (0x0 << 21)); setbits32(&ch[chn].ao.dummy_rd, 0x3 << 26); } dramc_dqs_precalculation_preset(); |