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| author | Rex-BC Chen <rex-bc.chen@mediatek.com> | 2022-03-03 19:16:04 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-03-10 15:04:34 +0000 |
| commit | 4fd80b286b6a868b4f45bad24af0870342d3fcae (patch) | |
| tree | f5fce4350eedccd697ebbbf60e2f0e554d694aa5 /src/soc/mediatek | |
| parent | 6277077d88bb2b144d62cf0d83ab8f055ae0a71b (diff) | |
| download | coreboot-4fd80b286b6a868b4f45bad24af0870342d3fcae.tar.gz coreboot-4fd80b286b6a868b4f45bad24af0870342d3fcae.tar.bz2 coreboot-4fd80b286b6a868b4f45bad24af0870342d3fcae.zip | |
soc/mediatek/mt8186: Modify internal capid to 0xE0
The mainboard may not be able to disable the internal cap, so we want
to set 0xe0 for all boards to minimize the internal cap. And a
mainboard implementation may choose XTAL with higher cload if the
frequency requirement is met, and the total capacitance can be tuned
externally for different boards.
BUG=b:218439447
TEST=set capid to 0xe0.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I2139e6b3456d7a50e3cdc8fc606e5f6ea3406044
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62563
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek')
| -rw-r--r-- | src/soc/mediatek/mt8186/rtc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/mediatek/mt8186/rtc.c b/src/soc/mediatek/mt8186/rtc.c index 2f78be8fa6b9..7375bc39e6d7 100644 --- a/src/soc/mediatek/mt8186/rtc.c +++ b/src/soc/mediatek/mt8186/rtc.c @@ -13,7 +13,7 @@ #include <soc/pmic_wrap.h> #include <timer.h> -#define MT8186_RTC_DXCO_CAPID 0xC0 +#define MT8186_RTC_DXCO_CAPID 0xE0 /* Initialize RTC setting of using DCXO clock */ static bool rtc_enable_dcxo(void) |