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| author | James Lo <james.lo@mediatek.corp-partner.google.com> | 2021-07-03 13:54:45 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-07-12 02:54:36 +0000 |
| commit | 543b32f60d939ccb196a7bbd46e8445b7fafb20c (patch) | |
| tree | 24876bdf6089499c9429ec45611747486900a009 /src/soc/mediatek | |
| parent | e46cd138ffad3bff6d6a68831c9c65b62e857ce6 (diff) | |
| download | coreboot-543b32f60d939ccb196a7bbd46e8445b7fafb20c.tar.gz coreboot-543b32f60d939ccb196a7bbd46e8445b7fafb20c.tar.bz2 coreboot-543b32f60d939ccb196a7bbd46e8445b7fafb20c.zip | |
soc/mediatek/mt8195: fine tune pmif spi hardware settings for stability
Update IO driving setting for pmif spi.
Signed-off-by: James Lo <james.lo@mediatek.corp-partner.google.com>
Change-Id: I48268cda8845a591592d8ca828ffe492e6dfe0ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56166
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek')
| -rw-r--r-- | src/soc/mediatek/mt8195/include/soc/iocfg.h | 1 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8195/pmif_spi.c | 6 |
2 files changed, 4 insertions, 3 deletions
diff --git a/src/soc/mediatek/mt8195/include/soc/iocfg.h b/src/soc/mediatek/mt8195/include/soc/iocfg.h index 8ca2f62f6279..f3524dcb9adf 100644 --- a/src/soc/mediatek/mt8195/include/soc/iocfg.h +++ b/src/soc/mediatek/mt8195/include/soc/iocfg.h @@ -63,5 +63,6 @@ check_member(mt8195_iocfg_bm_regs, tdsel_cfg1, 0x110); enum { IO_4_MA = 0x9, + IO_6_MA = 0x1b, }; #endif /* __SOC_MEDIATEK_MT8195_IOCFG_H__ */ diff --git a/src/soc/mediatek/mt8195/pmif_spi.c b/src/soc/mediatek/mt8195/pmif_spi.c index ddb217551696..eff4a21e8939 100644 --- a/src/soc/mediatek/mt8195/pmif_spi.c +++ b/src/soc/mediatek/mt8195/pmif_spi.c @@ -10,7 +10,7 @@ DEFINE_BITFIELD(PWRAP_SPI1_DRIVING, 5, 0) void pmif_spi_iocfg(void) { - /* Set SoC SPI IO driving strength to 4 mA */ - SET32_BITFIELDS(&mtk_iocfg_bm->drv_cfg1, PWRAP_SPI0_DRIVING, IO_4_MA); - SET32_BITFIELDS(&mtk_iocfg_bm->drv_cfg2, PWRAP_SPI1_DRIVING, IO_4_MA); + /* Set SoC SPI IO driving strength to 6 mA */ + SET32_BITFIELDS(&mtk_iocfg_bm->drv_cfg1, PWRAP_SPI0_DRIVING, IO_6_MA); + SET32_BITFIELDS(&mtk_iocfg_bm->drv_cfg2, PWRAP_SPI1_DRIVING, IO_6_MA); } |