soc/nvidia: Drop unneeded empty lines

Change-Id: I76430f5cd4b661aff85e2d21722f41c03362b1bd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44598
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

5 files changed, 0 insertions, 48 deletions

diff --git a/src/soc/nvidia/tegra124/dp.c b/src/soc/nvidia/tegra124/dp.c
index e3885bf83483..4155c34b2191 100644
--- a/src/soc/nvidia/tegra124/dp.c
+++ b/src/soc/nvidia/tegra124/dp.c
@@ -616,7 +616,6 @@ static int tegra_dc_dp_calc_config(struct tegra_dc_dp_data *dp,
 	if (link_cfg->hblank_sym < 0)
 		link_cfg->hblank_sym = 0;
 
-
 	/* Refer to dev_disp.ref for more information. */
 	/* # symbols/vblank = ((SetRasterBlankStart.X - */
 	/*                      SetRasterBlankEen.X - 25) * link_clk / pclk) */
diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c
index b7881de6a151..38a385cd29bc 100644
--- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c
+++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c
@@ -12,21 +12,15 @@ enum {
 	SYSCTR_CTLR_BASE = 0x700f0000
 };
 
-
-
 /* UP tag registers. */
 static uint32_t *up_tag_ptr = (void *)(UP_TAG_BASE + 0x0);
 enum {
 	UP_TAG_AVP = 0xaaaaaaaa
 };
 
-
-
 /* Timer registers. */
 static uint32_t *timer_us_ptr = (void *)(TIMER_BASE + 0x10);
 
-
-
 /* Clock and reset controller registers. */
 static uint32_t *clk_rst_rst_devices_l_ptr = (void *)(CLK_RST_BASE + 0x4);
 enum {
@@ -152,14 +146,9 @@ enum {
 	CLR_NONCPURESET = 0x1 << 29
 };
 
-
-
 /* Reset vector. */
-
 static uint32_t *evp_cpu_reset_ptr = (void *)(TEGRA_EVP_BASE + 0x100);
 
-
-
 /* Flow controller registers. */
 static uint32_t *flow_ctlr_halt_cop_events_ptr =
 	(void *)(FLOW_CTLR_BASE + 0x4);
@@ -185,7 +174,6 @@ enum {
 	RAM_REPAIR_STS = 0x1 << 1,
 };
 
-
 /* Power management controller registers. */
 enum {
 	PARTID_CRAIL = 0,
@@ -220,8 +208,6 @@ enum {
 	PMC_XOFS_MASK = 0x3f << PMC_XOFS_SHIFT
 };
 
-
-
 /* Memory controller registers. */
 static uint32_t *mc_video_protect_size_mb_ptr = (void *)(MC_CTLR_BASE + 0x64c);
 
@@ -232,8 +218,6 @@ enum {
 	VIDEO_PROTECT_ALLOW_TZ_WRITE_ACCESS = 0x1 << 1
 };
 
-
-
 /* System counter registers. */
 static uint32_t *sysctr_cntcr_ptr = (void *)(SYSCTR_CTLR_BASE + 0x0);
 enum {
@@ -243,10 +227,7 @@ enum {
 
 static uint32_t *sysctr_cntfid0_ptr = (void *)(SYSCTR_CTLR_BASE + 0x20);
 
-
-
 /* Utility functions. */
-
 static __always_inline void __noreturn halt(void)
 {
 	for (;;);
@@ -285,10 +266,7 @@ static void udelay(unsigned int usecs)
 		;
 }
 
-
-
 /* Accessors. */
-
 static int wakeup_on_lp(void)
 {
 	return !!(read32(pmc_ctlr_scratch4_ptr) & PMC_SCRATCH4_LP);
@@ -304,10 +282,7 @@ static unsigned int get_osc_freq(void)
 	return (read32(clk_rst_osc_ctrl_ptr) & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
 }
 
-
-
 /* Clock configuration. */
-
 static void config_oscillator(void)
 {
 	// Read oscillator drive strength from OSC_EDPD_OVER.XOFS and copy
@@ -416,10 +391,7 @@ static void enable_cpu_clocks(void)
 	write32(clk_rst_clk_enb_v_set_ptr, CLK_ENB_CPUG | CLK_ENB_CPULP);
 }
 
-
-
 /* Function unit configuration. */
-
 static void config_core_sight(void)
 {
 	// Enable the CoreSight clock.
@@ -449,10 +421,7 @@ static void config_mselect(void)
 	write32(clk_rst_rst_dev_v_clr_ptr, SWR_MSELECT_RST);
 }
 
-
-
 /* Resets. */
-
 static void clear_cpu_resets(void)
 {
 	// Take the non-cpu of the G and LP clusters out of reset.
@@ -471,10 +440,7 @@ static void clear_cpu_resets(void)
 		CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3);
 }
 
-
-
 /* RAM repair */
-
 void ram_repair(void)
 {
 	// Request Cluster0 RAM repair.
@@ -490,9 +456,7 @@ void ram_repair(void)
 		;
 }
 
-
 /* Power. */
-
 static void power_on_partition(unsigned int id)
 {
 	uint32_t bit = 0x1 << id;
@@ -544,10 +508,7 @@ static void power_on_main_cpu(void)
 	write32(pmc_ctlr_cpupwrgood_timer_ptr, orig_timer);
 }
 
-
-
 /* Entry point. */
-
 void lp0_resume(void)
 {
 	// If not on the AVP, reset.
@@ -608,10 +569,7 @@ void lp0_resume(void)
 		        FLOW_MODE_STOP | EVENT_JTAG);
 }
 
-
-
 /* Header. */
-
 extern uint8_t blob_data;
 extern uint8_t blob_data_size;
 extern uint8_t blob_total_size;
diff --git a/src/soc/nvidia/tegra124/sdram.c b/src/soc/nvidia/tegra124/sdram.c
index 30ceee6006d6..01444a1d0265 100644
--- a/src/soc/nvidia/tegra124/sdram.c
+++ b/src/soc/nvidia/tegra124/sdram.c
@@ -11,7 +11,6 @@
 #include <soc/sdram.h>
 #include <symbols.h>
 
-
 static void sdram_patch(uintptr_t addr, uint32_t value)
 {
 	if (addr)
diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c
index 18ea626d5710..3a078f8573cf 100644
--- a/src/soc/nvidia/tegra124/spi.c
+++ b/src/soc/nvidia/tegra124/spi.c
@@ -335,7 +335,6 @@ static void tegra_spi_wait(struct tegra_spi_channel *spi)
 		spi_delay(spi, dma_blk - count);
 }
 
-
 static int fifo_error(struct tegra_spi_channel *spi)
 {
 	return read32(&spi->regs->fifo_status) & SPI_FIFO_STATUS_ERR ? 1 : 0;
@@ -523,8 +522,6 @@ static void tegra_spi_dma_start(struct tegra_spi_channel *spi)
 	setbits32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA);
 	if (spi->dma_in)
 		dma_start(spi->dma_in);
-
-
 }
 
 static int tegra_spi_dma_finish(struct tegra_spi_channel *spi)
diff --git a/src/soc/nvidia/tegra124/uart.c b/src/soc/nvidia/tegra124/uart.c
index 4f24c0da6630..aba8dd954dba 100644
--- a/src/soc/nvidia/tegra124/uart.c
+++ b/src/soc/nvidia/tegra124/uart.c
@@ -5,7 +5,6 @@
 #include <console/uart.h>
 #include <drivers/uart/uart8250reg.h>
 
-
 struct tegra124_uart {
 	union {
 		uint32_t thr; // Transmit holding register.