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| author | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2018-11-26 15:04:46 +0100 |
|---|---|---|
| committer | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2018-11-30 10:26:56 +0000 |
| commit | 2af17af82981df83b91a58f88dc6aa143e6dee55 (patch) | |
| tree | 355a591acfc032b99a272427523ef073b2abafcb /src/soc/nvidia/tegra210/include/soc/memlayout.ld | |
| parent | aea00f496b1cf41fd5b568b4c6079c2ab76eafd4 (diff) | |
| download | coreboot-2af17af82981df83b91a58f88dc6aa143e6dee55.tar.gz coreboot-2af17af82981df83b91a58f88dc6aa143e6dee55.tar.bz2 coreboot-2af17af82981df83b91a58f88dc6aa143e6dee55.zip | |
security/vboot: Fix remaining measured boot issues
Makes vboot measured boot mode available for all boards.
* Increase Tegra210 and Rockchip3228 SRAM for
romstage/verstage.
* Add missing files for Intel apollolake and
AMD stoneyridge as TPM driver target.
Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/nvidia/tegra210/include/soc/memlayout.ld')
| -rw-r--r-- | src/soc/nvidia/tegra210/include/soc/memlayout.ld | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout.ld b/src/soc/nvidia/tegra210/include/soc/memlayout.ld index c1c581bf7151..d807c0659974 100644 --- a/src/soc/nvidia/tegra210/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra210/include/soc/memlayout.ld @@ -28,18 +28,18 @@ SECTIONS { SRAM_START(0x40000000) - PRERAM_CBMEM_CONSOLE(0x40000000, 8K) - PRERAM_CBFS_CACHE(0x40002000, 36K) - VBOOT2_WORK(0x4000B000, 12K) + PRERAM_CBMEM_CONSOLE(0x40000000, 4K) + PRERAM_CBFS_CACHE(0x40001000, 36K) + VBOOT2_WORK(0x4000A000, 12K) #if ENV_ARM64 - STACK(0x4000E000, 3K) + STACK(0x4000D000, 3K) #else /* AVP gets a separate stack to avoid any chance of handoff races. */ - STACK(0x4000EC00, 3K) + STACK(0x4000DC00, 3K) #endif - TIMESTAMP(0x4000F800, 2K) - BOOTBLOCK(0x40010000, 28K) - VERSTAGE(0x40017000, 64K) - ROMSTAGE(0x40027000, 100K) + TIMESTAMP(0x4000E800, 2K) + BOOTBLOCK(0x4000F000, 28K) + VERSTAGE(0x40016000, 64K) + ROMSTAGE(0x40026000, 104K) SRAM_END(0x40040000) DRAM_START(0x80000000) |