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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-05-22 12:51:27 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-04 08:52:13 +0000 |
| commit | 448d9fb4310eb8c390020c64af703060ab3545a6 (patch) | |
| tree | a2b820d5aee80f3de5798584c257c9ec894ffa57 /src/soc/nvidia/tegra210 | |
| parent | 7154ef2fe155ce34517c8f893ffec6bc1500e6ac (diff) | |
| download | coreboot-448d9fb4310eb8c390020c64af703060ab3545a6.tar.gz coreboot-448d9fb4310eb8c390020c64af703060ab3545a6.tar.bz2 coreboot-448d9fb4310eb8c390020c64af703060ab3545a6.zip | |
src: Use "foo *bar" instead of "foo* bar"
Change-Id: Ib2bb6cc80ac2bdc389c60c7ffac4bba937f0fca8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/nvidia/tegra210')
| -rw-r--r-- | src/soc/nvidia/tegra210/clock.c | 2 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/include/soc/clock.h | 3 |
2 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/nvidia/tegra210/clock.c b/src/soc/nvidia/tegra210/clock.c index 277ba2705033..51cfc8b2c8d1 100644 --- a/src/soc/nvidia/tegra210/clock.c +++ b/src/soc/nvidia/tegra210/clock.c @@ -646,7 +646,7 @@ void clock_init(void) graphics_pll(); } -void clock_grp_enable_clear_reset(u32 val, u32* clk_enb_set_reg, +void clock_grp_enable_clear_reset(u32 val, u32 *clk_enb_set_reg, u32 *rst_dev_clr_reg) { write32(clk_enb_set_reg, val); diff --git a/src/soc/nvidia/tegra210/include/soc/clock.h b/src/soc/nvidia/tegra210/include/soc/clock.h index f3a63c8e5e37..50d72603ee7b 100644 --- a/src/soc/nvidia/tegra210/include/soc/clock.h +++ b/src/soc/nvidia/tegra210/include/soc/clock.h @@ -433,7 +433,8 @@ void clock_disable_regs(u32 bits[DEV_CONFIG_BLOCKS]); void clock_set_reset_regs(u32 bits[DEV_CONFIG_BLOCKS]); void clock_clr_reset_regs(u32 bits[DEV_CONFIG_BLOCKS]); void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x, u32 y); -void clock_grp_enable_clear_reset(u32 val, u32* clk_enb_set_reg, u32* rst_dev_clr_reg); +void clock_grp_enable_clear_reset(u32 val, u32 *clk_enb_set_reg, + u32 *rst_dev_clr_reg); void clock_reset_l(u32 l); void clock_reset_h(u32 h); void clock_reset_u(u32 u); |