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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2021-01-16 14:55:30 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-18 07:34:48 +0000 |
| commit | b9d95c5f643650db7b1b25fa000ccf2b25f3b634 (patch) | |
| tree | 5677ff9f4f5e92341f6c54c82bfe99971965dbeb /src/soc/nvidia/tegra210 | |
| parent | a83369828073f455a149a90e3f33d4be6ff3b5a9 (diff) | |
| download | coreboot-b9d95c5f643650db7b1b25fa000ccf2b25f3b634.tar.gz coreboot-b9d95c5f643650db7b1b25fa000ccf2b25f3b634.tar.bz2 coreboot-b9d95c5f643650db7b1b25fa000ccf2b25f3b634.zip | |
soc/nvidia/tegra210/spi.c: Remove repeated word
Change-Id: Iea0c973b2bd493eb69ef76289b5b4fc66ac622f6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Diffstat (limited to 'src/soc/nvidia/tegra210')
| -rw-r--r-- | src/soc/nvidia/tegra210/spi.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/nvidia/tegra210/spi.c b/src/soc/nvidia/tegra210/spi.c index 66f9fd8c93f8..f8db110f7afe 100644 --- a/src/soc/nvidia/tegra210/spi.c +++ b/src/soc/nvidia/tegra210/spi.c @@ -639,7 +639,7 @@ static int xfer_setup(struct tegra_spi_channel *spi, void *buf, * When we enable caching we'll need to clean/invalidate portions of * memory. So we need to be careful about memory alignment. Also, DMA * likes to operate on 4-bytes at a time on the AHB side. So for - * example, if we only want to receive 1 byte, 4 bytes will be be + * example, if we only want to receive 1 byte, 4 bytes will be * written in memory even if those extra 3 bytes are beyond the length * we want. * |