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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-05-07 09:04:46 -0700 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2016-05-09 18:45:44 +0200 |
| commit | 6ec72c9b4f4a903d9a451bc17629e679399aa9ee (patch) | |
| tree | 815f70ba90e3646911d8380d803c823f1fefb507 /src/soc/nvidia | |
| parent | 148762110c8a00c88b8e0326ec69dc7392bf3739 (diff) | |
| download | coreboot-6ec72c9b4f4a903d9a451bc17629e679399aa9ee.tar.gz coreboot-6ec72c9b4f4a903d9a451bc17629e679399aa9ee.tar.bz2 coreboot-6ec72c9b4f4a903d9a451bc17629e679399aa9ee.zip | |
drivers/uart: Use uart_platform_refclk for all UART models
Allow the platform to override the input clock for the UART by
implementing the routine uart_platform_refclk and setting the Kconfig
value UART_OVERRIDE_REFCLK. Provide a default uart_platform_refclk
routine which is disabled when UART_OVERRIDE_REFCLK is selected. This
works around ROMCC not supporting weak routines.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file:
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
UEFIPAYLOAD.fd
* Testing is successful when CorebootPayloadPkg is able to properly
initialize the serial port without using built-in values.
Change-Id: If4afc45a828e5ba935fecb6d95b239625e912d14
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14612
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/nvidia')
| -rw-r--r-- | src/soc/nvidia/tegra132/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig index 502e7c4c72c3..08ed47567beb 100644 --- a/src/soc/nvidia/tegra132/Kconfig +++ b/src/soc/nvidia/tegra132/Kconfig @@ -13,6 +13,7 @@ config SOC_NVIDIA_TEGRA132 select HAVE_HARD_RESET select HAVE_UART_SPECIAL select GENERIC_GPIO_LIB + select UART_OVERRIDE_REFCLK if SOC_NVIDIA_TEGRA132 |