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| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-03-24 00:11:07 +0100 |
|---|---|---|
| committer | Martin Roth <martin.roth@amd.corp-partner.google.com> | 2022-11-10 15:33:32 +0000 |
| commit | 961e09c631a74566a9567f887696f073bce35984 (patch) | |
| tree | 4548a2170bc9ce6387c8321e5b5335ee424a12e0 /src/soc/nvidia | |
| parent | 1b2c03b9d84c110b4a895a2fcdc26d55888f93e5 (diff) | |
| download | coreboot-961e09c631a74566a9567f887696f073bce35984.tar.gz coreboot-961e09c631a74566a9567f887696f073bce35984.tar.bz2 coreboot-961e09c631a74566a9567f887696f073bce35984.zip | |
soc/nvidia/tegra124: Fix building with clang
This kind of allocation without '=' is not working with clang.
Change-Id: I2d3e9eb44c3e0e25e5a67c5386e5ddde1487cc74
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63063
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/nvidia')
| -rw-r--r-- | src/soc/nvidia/tegra124/clock.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index a2427fe70b46..f8a232f875fa 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -90,35 +90,35 @@ struct { struct pllcx_dividers plldp; /* target; 270 MHz */ /* PLLDP treats p differently (OUT = VCO / (p + 1) for p < 6). */ } static const osc_table[16] = { - [OSC_FREQ_12]{ + [OSC_FREQ_12] = { .khz = 12000, .pllx = {.n = TEGRA_PLLX_KHZ / 12000, .m = 1, .p = 0}, .pllc = {.n = 50, .m = 1, .p = 0}, .pllu = {.n = 960, .m = 12, .p = 0, .cpcon = 12, .lfcon = 2}, .plldp = {.n = 90, .m = 1, .p = 3}, }, - [OSC_FREQ_13]{ + [OSC_FREQ_13] = { .khz = 13000, .pllx = {.n = TEGRA_PLLX_KHZ / 13000, .m = 1, .p = 0}, .pllc = {.n = 46, .m = 1, .p = 0}, /* 598.0 MHz */ .pllu = {.n = 960, .m = 13, .p = 0, .cpcon = 12, .lfcon = 2}, .plldp = {.n = 83, .m = 1, .p = 3}, /* 269.8 MHz */ }, - [OSC_FREQ_16P8]{ + [OSC_FREQ_16P8] = { .khz = 16800, .pllx = {.n = TEGRA_PLLX_KHZ / 16800, .m = 1, .p = 0}, .pllc = {.n = 71, .m = 1, .p = 1}, /* 596.4 MHz */ .pllu = {.n = 400, .m = 7, .p = 0, .cpcon = 5, .lfcon = 2}, .plldp = {.n = 64, .m = 1, .p = 3}, /* 268.8 MHz */ }, - [OSC_FREQ_19P2]{ + [OSC_FREQ_19P2] = { .khz = 19200, .pllx = {.n = TEGRA_PLLX_KHZ / 19200, .m = 1, .p = 0}, .pllc = {.n = 62, .m = 1, .p = 1}, /* 595.2 MHz */ .pllu = {.n = 200, .m = 4, .p = 0, .cpcon = 3, .lfcon = 2}, .plldp = {.n = 56, .m = 1, .p = 3}, /* 268.8 MHz */ }, - [OSC_FREQ_26]{ + [OSC_FREQ_26] = { .khz = 26000, .pllx = {.n = TEGRA_PLLX_KHZ / 26000, .m = 1, .p = 0}, .pllc = {.n = 23, .m = 1, .p = 0}, /* 598.0 MHz */ @@ -127,14 +127,14 @@ struct { }, /* These oscillators get predivided as PLL inputs... n/m/p divisors for * 38.4 should always match 19.2, and 48 should always match 12. */ - [OSC_FREQ_38P4]{ + [OSC_FREQ_38P4] = { .khz = 38400, .pllx = {.n = TEGRA_PLLX_KHZ / 19200, .m = 1, .p = 0}, .pllc = {.n = 62, .m = 1, .p = 1}, /* 595.2 MHz */ .pllu = {.n = 200, .m = 4, .p = 0, .cpcon = 3, .lfcon = 2}, .plldp = {.n = 56, .m = 1, .p = 3}, /* 268.8 MHz */ }, - [OSC_FREQ_48]{ + [OSC_FREQ_48] = { .khz = 48000, .pllx = {.n = TEGRA_PLLX_KHZ / 12000, .m = 1, .p = 0}, .pllc = {.n = 50, .m = 1, .p = 0}, |