diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-03-15 14:56:16 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-16 21:29:53 +0000 |
| commit | fff20212afe2c83af90dbec39d112a31d34b6658 (patch) | |
| tree | ed5d0de6ca1aac63822c479428e1ca63bdf14748 /src/soc/nvidia | |
| parent | 97a0d61f0d1d5a9280ba72e2e50d87e4b853777f (diff) | |
| download | coreboot-fff20212afe2c83af90dbec39d112a31d34b6658.tar.gz coreboot-fff20212afe2c83af90dbec39d112a31d34b6658.tar.bz2 coreboot-fff20212afe2c83af90dbec39d112a31d34b6658.zip | |
Use the fallthrough statement in switch loops
Clang does not seem to work with 'fall through' in comments.
Change-Id: Idcbe373be33ef7247548f856bfaba7ceb7f749b5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/nvidia')
| -rw-r--r-- | src/soc/nvidia/tegra124/sor.c | 8 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/sor.c | 7 |
2 files changed, 8 insertions, 7 deletions
diff --git a/src/soc/nvidia/tegra124/sor.c b/src/soc/nvidia/tegra124/sor.c index 9e56c68c08c7..9d3422786a8b 100644 --- a/src/soc/nvidia/tegra124/sor.c +++ b/src/soc/nvidia/tegra124/sor.c @@ -220,10 +220,10 @@ static int tegra_dc_sor_power_dplanes(struct tegra_dc_sor_data *sor, case 4: reg_val |= (NV_SOR_DP_PADCTL_PD_TXD_3_NO | NV_SOR_DP_PADCTL_PD_TXD_2_NO); - /* fall through */ + __fallthrough; case 2: reg_val |= NV_SOR_DP_PADCTL_PD_TXD_1_NO; - /* fall through */ + __fallthrough; case 1: reg_val |= NV_SOR_DP_PADCTL_PD_TXD_0_NO; break; @@ -891,10 +891,10 @@ void tegra_sor_precharge_lanes(struct tegra_dc_sor_data *sor) case 4: val |= (NV_SOR_DP_PADCTL_PD_TXD_3_NO | NV_SOR_DP_PADCTL_PD_TXD_2_NO); - /* fall through */ + __fallthrough; case 2: val |= NV_SOR_DP_PADCTL_PD_TXD_1_NO; - /* fall through */ + __fallthrough; case 1: val |= NV_SOR_DP_PADCTL_PD_TXD_0_NO; break; diff --git a/src/soc/nvidia/tegra210/sor.c b/src/soc/nvidia/tegra210/sor.c index fe89d147aa20..3b0c128d49fb 100644 --- a/src/soc/nvidia/tegra210/sor.c +++ b/src/soc/nvidia/tegra210/sor.c @@ -222,9 +222,10 @@ static int tegra_dc_sor_power_dplanes(struct tegra_dc_sor_data *sor, case 4: reg_val |= (NV_SOR_DP_PADCTL_PD_TXD_3_NO | NV_SOR_DP_PADCTL_PD_TXD_2_NO); - /* fall through */ + fallthrough; case 2: reg_val |= NV_SOR_DP_PADCTL_PD_TXD_1_NO; + fallthrough; case 1: reg_val |= NV_SOR_DP_PADCTL_PD_TXD_0_NO; break; @@ -889,10 +890,10 @@ void tegra_sor_precharge_lanes(struct tegra_dc_sor_data *sor) case 4: val |= (NV_SOR_DP_PADCTL_PD_TXD_3_NO | NV_SOR_DP_PADCTL_PD_TXD_2_NO); - /* fall through */ + fallthrough; case 2: val |= NV_SOR_DP_PADCTL_PD_TXD_1_NO; - /* fall through */ + fallthrough; case 1: val |= NV_SOR_DP_PADCTL_PD_TXD_0_NO; break; |