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| author | T Michael Turney <mturney@codeaurora.org> | 2019-11-27 19:28:23 -0800 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2020-04-21 21:53:08 +0000 |
| commit | cea0d9c0ffc06359b01310c0dd728b4527c0013d (patch) | |
| tree | 4bf61e0d7525efc8bad62fc14c7b73bfc6699a19 /src/soc/qualcomm/sc7180/bootblock.c | |
| parent | 9d25207aaf93cb8052910f11fc1febd7865fb6e9 (diff) | |
| download | coreboot-cea0d9c0ffc06359b01310c0dd728b4527c0013d.tar.gz coreboot-cea0d9c0ffc06359b01310c0dd728b4527c0013d.tar.bz2 coreboot-cea0d9c0ffc06359b01310c0dd728b4527c0013d.zip | |
sc7180: Add QUPv3 FW load & config
UART driver requires firmware loading
Developer/Reviewer, be aware of this patch from Napali:
https://review.coreboot.org/c/coreboot/+/25372/78
https://review.coreboot.org/c/coreboot/+/27483/58
Change-Id: I4d91dd10488931247f81a87b0bdcc598f4bceb31
Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/qualcomm/sc7180/bootblock.c')
| -rw-r--r-- | src/soc/qualcomm/sc7180/bootblock.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/qualcomm/sc7180/bootblock.c b/src/soc/qualcomm/sc7180/bootblock.c index 29348c2a2480..9cecb4f4f512 100644 --- a/src/soc/qualcomm/sc7180/bootblock.c +++ b/src/soc/qualcomm/sc7180/bootblock.c @@ -16,10 +16,12 @@ #include <soc/clock.h> #include <soc/mmu.h> #include <soc/qspi.h> +#include <soc/qupv3_config.h> void bootblock_soc_init(void) { sc7180_mmu_init(); clock_init(); quadspi_init(25 * MHz); + qupv3_fw_init(); } |