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| author | Shelley Chen <shchen@google.com> | 2022-05-11 18:29:19 -0700 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2022-05-31 22:19:02 +0000 |
| commit | 363202b43589ec240c4a0c8f5b449fbd5c1333f8 (patch) | |
| tree | 100b1fce60d7bc89ef6d0240c4fc45144ae12af5 /src/soc/qualcomm/sc7280 | |
| parent | 84d54d40b8b54ec036c2e597c404aaeb98746e63 (diff) | |
| download | coreboot-363202b43589ec240c4a0c8f5b449fbd5c1333f8.tar.gz coreboot-363202b43589ec240c4a0c8f5b449fbd5c1333f8.tar.bz2 coreboot-363202b43589ec240c4a0c8f5b449fbd5c1333f8.zip | |
soc/qualcomm: Increase SPI frequency to 75 MHz
Increase frequency of sc7280 to 75 MHz. Setting the delay to 1/8 of
a cycle as a result of experimentation.
BUG=b:190231148
BRANCH=None
TEST=Make sure that herobrine board boots
HW Engineer measured SPI frequency and verified running at 75 MHz
Signed-off-by: Shelley Chen <shchen@google.com>
Change-Id: I3cf5a7c85f12800a11ece397a354349f2a0a235f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64673
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/qualcomm/sc7280')
| -rw-r--r-- | src/soc/qualcomm/sc7280/bootblock.c | 7 | ||||
| -rw-r--r-- | src/soc/qualcomm/sc7280/clock.c | 10 |
2 files changed, 16 insertions, 1 deletions
diff --git a/src/soc/qualcomm/sc7280/bootblock.c b/src/soc/qualcomm/sc7280/bootblock.c index bdabea1fbb49..0926127baff5 100644 --- a/src/soc/qualcomm/sc7280/bootblock.c +++ b/src/soc/qualcomm/sc7280/bootblock.c @@ -8,6 +8,11 @@ void bootblock_soc_init(void) { clock_init(); - quadspi_init(50000 * KHz); + /* + * Through experimentation, we have determined + * that a delay of 1/8 cycle is best for herobrine. + * See b/190231148 + */ + quadspi_init(75000 * KHz, 1); qupv3_fw_init(); } diff --git a/src/soc/qualcomm/sc7280/clock.c b/src/soc/qualcomm/sc7280/clock.c index 4441e480830c..7b017c4d806c 100644 --- a/src/soc/qualcomm/sc7280/clock.c +++ b/src/soc/qualcomm/sc7280/clock.c @@ -28,6 +28,16 @@ static struct clock_freq_config qspi_core_cfg[] = { .div = QCOM_CLOCK_DIV(3), }, { + .hz = 240 * MHz, + .src = SRC_GPLL0_MAIN_600MHZ, + .div = QCOM_CLOCK_DIV(2.5), + }, + { + .hz = 300 * MHz, + .src = SRC_GPLL0_MAIN_600MHZ, + .div = QCOM_CLOCK_DIV(2), + }, + { .hz = 400 * MHz, .src = SRC_GPLL0_MAIN_600MHZ, .div = QCOM_CLOCK_DIV(1.5), |