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| author | huang lin <hl@rock-chips.com> | 2015-01-26 21:04:55 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-17 09:26:09 +0200 |
| commit | ee28c86ccde1427e5f9aa4a110ee7d7f2629bc3c (patch) | |
| tree | 3790ce6abda86308631a138d73dd937dd8d7e5f7 /src/soc/rockchip/rk3288/Makefile.inc | |
| parent | d37bc75632867e547ad4c8b1f333a1b5247c88e5 (diff) | |
| download | coreboot-ee28c86ccde1427e5f9aa4a110ee7d7f2629bc3c.tar.gz coreboot-ee28c86ccde1427e5f9aa4a110ee7d7f2629bc3c.tar.bz2 coreboot-ee28c86ccde1427e5f9aa4a110ee7d7f2629bc3c.zip | |
rk3288: detect sdram size at runtime
we use Kconfig define sdram size before, but there may use
different sdram size in the same overlay, so we must detect
sdram size at runtime now. If we use 4G byte sdram, we can
use[0x00000000:0xff000000], since the [0xff000000:0xffffffff]
is the register space.
BUG=chrome-os-partner:35521
TEST=Boot from mighty
BRANCH=None
Change-Id: I7a167c268483743c3eaed8b71c7ec545a688270c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ad4f27dd08c467888eee87e3d9c4ab3077751898
Original-Change-Id: Ib32aed50c9cae6db495ff3bab28266de91f3e73b
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/243139
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9734
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/rockchip/rk3288/Makefile.inc')
| -rw-r--r-- | src/soc/rockchip/rk3288/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc index c7e52a9f3e51..c4a77e0fcde7 100644 --- a/src/soc/rockchip/rk3288/Makefile.inc +++ b/src/soc/rockchip/rk3288/Makefile.inc @@ -57,6 +57,7 @@ ramstage-y += timer.c ramstage-y += i2c.c ramstage-y += clock.c ramstage-y += spi.c +ramstage-y += sdram.c ramstage-y += gpio.c ramstage-y += rk808.c ramstage-y += pwm.c |