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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-10-13 11:13:59 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-10-19 07:11:52 +0000 |
| commit | 78efb84509080508d71c1348dd39718bdec90a61 (patch) | |
| tree | 7fd574eda662d922c06718e891963dd119c17daa /src/soc/rockchip/rk3288 | |
| parent | 59143bbebdcb1e0c12af720858c1d73af8e4d680 (diff) | |
| download | coreboot-78efb84509080508d71c1348dd39718bdec90a61.tar.gz coreboot-78efb84509080508d71c1348dd39718bdec90a61.tar.bz2 coreboot-78efb84509080508d71c1348dd39718bdec90a61.zip | |
soc/rockchip/rk3288/gpio.c: Use GPIOx_BASE macros
Change-Id: Idd16454884d6d847eb7ad071ff1d3e0c0de53e5b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/rockchip/rk3288')
| -rw-r--r-- | src/soc/rockchip/rk3288/gpio.c | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/src/soc/rockchip/rk3288/gpio.c b/src/soc/rockchip/rk3288/gpio.c index 885b41902e33..ed09d02fc4da 100644 --- a/src/soc/rockchip/rk3288/gpio.c +++ b/src/soc/rockchip/rk3288/gpio.c @@ -1,21 +1,22 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <gpio.h> +#include <soc/addressmap.h> #include <soc/gpio.h> #include <soc/grf.h> #include <soc/pmu.h> #include <soc/soc.h> struct rockchip_gpio_regs *gpio_port[] = { - (struct rockchip_gpio_regs *)0xff750000, - (struct rockchip_gpio_regs *)0xff780000, - (struct rockchip_gpio_regs *)0xff790000, - (struct rockchip_gpio_regs *)0xff7a0000, - (struct rockchip_gpio_regs *)0xff7b0000, - (struct rockchip_gpio_regs *)0xff7c0000, - (struct rockchip_gpio_regs *)0xff7d0000, - (struct rockchip_gpio_regs *)0xff7e0000, - (struct rockchip_gpio_regs *)0xff7f0000 + (struct rockchip_gpio_regs *)GPIO0_BASE, + (struct rockchip_gpio_regs *)GPIO1_BASE, + (struct rockchip_gpio_regs *)GPIO2_BASE, + (struct rockchip_gpio_regs *)GPIO3_BASE, + (struct rockchip_gpio_regs *)GPIO4_BASE, + (struct rockchip_gpio_regs *)GPIO5_BASE, + (struct rockchip_gpio_regs *)GPIO6_BASE, + (struct rockchip_gpio_regs *)GPIO7_BASE, + (struct rockchip_gpio_regs *)GPIO8_BASE }; #define PMU_GPIO_PORT 0 |