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| author | Lin Huang <hl@rock-chips.com> | 2016-06-28 15:21:20 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-07-12 00:27:52 +0200 |
| commit | bdd06de15d3edc1398db72591f1a173fee5befab (patch) | |
| tree | 78d5612f9ae0ae5a9131814c67fcd248c5de8c76 /src/soc/rockchip/rk3399/bootblock.c | |
| parent | 3d703bcc70c346ba1edad1b8f8391e62814f3ceb (diff) | |
| download | coreboot-bdd06de15d3edc1398db72591f1a173fee5befab.tar.gz coreboot-bdd06de15d3edc1398db72591f1a173fee5befab.tar.bz2 coreboot-bdd06de15d3edc1398db72591f1a173fee5befab.zip | |
rockchip/rk3399: initialize apll_b
coreboot boots from the little core, and doesn't use the big core for
now, but if apll_b is set to the default 24MHz, it will take a long time
to enable the big core. This will cause a watchdog crash, so apll_b
initialization to 600MHz needs to be done in coreboot.
BRANCH=none
BUG=chrome-os-partner:54817
TEST=Pick CL:353762 and see big CPU clocks look right
TEST=Boot from Gru and see no cpufreq warnings
Change-Id: Ie45cd2271555942e4321e9a9e523dc10f63d8107
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id:
Original-Change-Id: I20b8b591db3171e27740d85edce11f9e8797d849
Original-Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Original-Commit-Id: 16bc916174042620bebe19ae73d241002491aecc
Original-Original-Change-Id: Id3487138b383b6643ba7e3ce1eae501a6622da10
Original-Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Original-Reviewed-on: https://chromium-review.googlesource.com/356399
Original-Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/15583
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/rockchip/rk3399/bootblock.c')
| -rw-r--r-- | src/soc/rockchip/rk3399/bootblock.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/rockchip/rk3399/bootblock.c b/src/soc/rockchip/rk3399/bootblock.c index 3e95a172676f..4f85e94ff4fc 100644 --- a/src/soc/rockchip/rk3399/bootblock.c +++ b/src/soc/rockchip/rk3399/bootblock.c @@ -22,7 +22,7 @@ void bootblock_soc_init(void) { rkclk_init(); - rkclk_configure_cpu(APLL_600_MHZ); + rkclk_configure_cpu(APLL_600_MHZ, false); /* all ddr range non-secure */ write32(&rk3399_pmusgrf->ddr_rgn_con[16], 0xff << 16 | 0); |