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| author | Patrick Georgi <patrick@coreboot.org> | 2023-10-07 11:16:43 +0200 |
|---|---|---|
| committer | Patrick Georgi <patrick@coreboot.org> | 2023-10-11 12:08:22 +0000 |
| commit | 42f15054b178efe9a4d1c8a4e0c203d1aa4aad01 (patch) | |
| tree | e1702953813d9c5c0930be4aca3d95b2aeecde00 /src/soc/rockchip | |
| parent | c666a916112aece345da57a0b4f3bafc43234ee7 (diff) | |
| download | coreboot-42f15054b178efe9a4d1c8a4e0c203d1aa4aad01.tar.gz coreboot-42f15054b178efe9a4d1c8a4e0c203d1aa4aad01.tar.bz2 coreboot-42f15054b178efe9a4d1c8a4e0c203d1aa4aad01.zip | |
memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere
This is in preparation of a larger heap. I went for 2MB because why not?
Change-Id: I51f999a10ba894a7f2f5fce224d30bf914107c38
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/rockchip')
| -rw-r--r-- | src/soc/rockchip/rk3288/memlayout.ld | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/rockchip/rk3288/memlayout.ld b/src/soc/rockchip/rk3288/memlayout.ld index 5e35a064b9f3..ea69a427046f 100644 --- a/src/soc/rockchip/rk3288/memlayout.ld +++ b/src/soc/rockchip/rk3288/memlayout.ld @@ -10,7 +10,7 @@ SECTIONS { DRAM_START(0x00000000) - RAMSTAGE(0x00200000, 128K) + RAMSTAGE(0x00200000, 2M) POSTRAM_CBFS_CACHE(0x01000000, 1M) DMA_COHERENT(0x10000000, 2M) FRAMEBUFFER(0x10800000, 8M) |