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| author | Martin Roth <martin@coreboot.org> | 2021-10-01 14:53:22 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-10-05 18:07:08 +0000 |
| commit | 26f97f9532933da3c1d72a7918c8a24457bbc1c0 (patch) | |
| tree | 8c25279e58ef541fae197ec193f5642a9b21b2d4 /src/soc/samsung/exynos5420 | |
| parent | 50863daef8ed75c0cb3dfd375e7622c898de5821 (diff) | |
| download | coreboot-26f97f9532933da3c1d72a7918c8a24457bbc1c0.tar.gz coreboot-26f97f9532933da3c1d72a7918c8a24457bbc1c0.tar.bz2 coreboot-26f97f9532933da3c1d72a7918c8a24457bbc1c0.zip | |
src/soc to src/superio: Fix spelling errors
These issues were found and fixed by codespell, a useful tool for
finding spelling errors.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/samsung/exynos5420')
| -rw-r--r-- | src/soc/samsung/exynos5420/dmc_init_ddr3.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/samsung/exynos5420/dmc_init_ddr3.c b/src/soc/samsung/exynos5420/dmc_init_ddr3.c index b1eae8981786..a187f6e090dd 100644 --- a/src/soc/samsung/exynos5420/dmc_init_ddr3.c +++ b/src/soc/samsung/exynos5420/dmc_init_ddr3.c @@ -147,7 +147,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) if (reset) { /* Send NOP, MRS and ZQINIT commands. * Sending MRS command will reset the DRAM. We should not be - * reseting the DRAM after resume, this will lead to memory + * resetting the DRAM after resume, this will lead to memory * corruption as DRAM content is lost after DRAM reset. */ dmc_config_mrs(mem, exynos_drex0); |