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| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-05-12 21:16:41 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2017-09-23 11:06:25 +0000 |
| commit | b29078e4015bbc3e8cf00ba64f0799c087546563 (patch) | |
| tree | 57c64e181ce902a4babcd7b031f699f6db5d93bd /src/soc/samsung | |
| parent | 1850aa6df6a324960bd0873277660d84562cdb61 (diff) | |
| download | coreboot-b29078e4015bbc3e8cf00ba64f0799c087546563.tar.gz coreboot-b29078e4015bbc3e8cf00ba64f0799c087546563.tar.bz2 coreboot-b29078e4015bbc3e8cf00ba64f0799c087546563.zip | |
mb/*/*: Remove rtc nvram configurable baud rate
There have been discussions about removing this since it does not seem
to be used much and only creates troubles for boards without defaults,
not to mention that it was configurable on many boards that do not
even feature uart.
It is still possible to configure the baudrate through the Kconfig
option.
Change-Id: I71698d9b188eeac73670b18b757dff5fcea0df41
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/samsung')
| -rw-r--r-- | src/soc/samsung/exynos5250/uart.c | 4 | ||||
| -rw-r--r-- | src/soc/samsung/exynos5420/uart.c | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/samsung/exynos5250/uart.c b/src/soc/samsung/exynos5250/uart.c index 07f1e34cceee..7ad6cbe6d9b8 100644 --- a/src/soc/samsung/exynos5250/uart.c +++ b/src/soc/samsung/exynos5250/uart.c @@ -61,7 +61,7 @@ static void serial_setbrg_dev(struct s5p_uart *uart) // All UARTs share the same clock. uclk = clock_get_periph_rate(PERIPH_ID_UART3); - val = uclk / default_baudrate(); + val = uclk / CONFIG_TTYS0_BAUD; write32(&uart->ubrdiv, val / 16 - 1); @@ -191,7 +191,7 @@ void uart_fill_lb(void *data) struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); - serial.baud = default_baudrate(); + serial.baud = CONFIG_TTYS0_BAUD; serial.regwidth = 4; lb_add_serial(&serial, data); diff --git a/src/soc/samsung/exynos5420/uart.c b/src/soc/samsung/exynos5420/uart.c index 6f54c003ba4f..a38be07d131f 100644 --- a/src/soc/samsung/exynos5420/uart.c +++ b/src/soc/samsung/exynos5420/uart.c @@ -61,7 +61,7 @@ static void serial_setbrg_dev(struct s5p_uart *uart) // All UARTs share the same clock. uclk = clock_get_periph_rate(PERIPH_ID_UART3); - val = uclk / default_baudrate(); + val = uclk / CONFIG_TTYS0_BAUD; write32(&uart->ubrdiv, val / 16 - 1); @@ -182,7 +182,7 @@ void uart_fill_lb(void *data) struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); - serial.baud = default_baudrate(); + serial.baud = CONFIG_TTYS0_BAUD; serial.regwidth = 4; serial.input_hertz = uart_platform_refclk(); serial.uart_pci_addr = 0; |