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authorPhilipp Hug <philipp@hug.cx>2018-09-13 22:16:36 +0200
committerRonald G. Minnich <rminnich@gmail.com>2018-09-14 09:51:02 +0000
commit374d992fc831300377216fd3f7c3137d4b53ab36 (patch)
tree73f0c880bb41c08b861f0e8796f7cf3223616b73 /src/soc/sifive/fu540/Makefile.inc
parentc014ef59191c512100a0596f998ffb9926fc8eb0 (diff)
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soc/sifive/fu540: Switch clock to 1GHz in romstage
Invoke clock_init in romstage for SiFive Unleashed. Change-Id: Ib869762d557e8fdf4c83a53698102df116d80389 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/28602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/soc/sifive/fu540/Makefile.inc')
-rw-r--r--src/soc/sifive/fu540/Makefile.inc2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/sifive/fu540/Makefile.inc b/src/soc/sifive/fu540/Makefile.inc
index b991783b6c60..ed1836ed67a9 100644
--- a/src/soc/sifive/fu540/Makefile.inc
+++ b/src/soc/sifive/fu540/Makefile.inc
@@ -22,6 +22,7 @@ romstage-y += uart.c
romstage-y += media.c
romstage-y += sdram.c
romstage-y += otp.c
+romstage-y += clock.c
ramstage-y += uart.c
ramstage-y += clint.c
@@ -29,6 +30,7 @@ ramstage-y += media.c
ramstage-y += sdram.c
ramstage-y += cbmem.c
ramstage-y += otp.c
+ramstage-y += clock.c
CPPFLAGS_common += -Isrc/soc/sifive/fu540/include