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authorXiang Wang <wxjstz@126.com>2019-05-29 15:39:48 +0800
committerPatrick Rudolph <siro@das-labor.org>2019-08-12 08:35:17 +0000
commitf4e158337683640220e3662fd6ca135bd3bad31b (patch)
treeecf48ac9a68ffe399fd64b40986cc53754470651 /src/soc/sifive/fu540/Makefile.inc
parent8adaffcbed6372970f34b85177bd42bb508d03e2 (diff)
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soc/sifive/fu540: add code for spi and map flash to memory spaces
SiFive's ZSBL has initialized flash, but only 16MB of space is available. 1. add code for spi 2. add code to map flash to memory spaces Change-Id: I106688c65ac7dd70be7479dc4691797b700682d9 Signed-off-by: Xiang Wang <merle@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/soc/sifive/fu540/Makefile.inc')
-rw-r--r--src/soc/sifive/fu540/Makefile.inc6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/sifive/fu540/Makefile.inc b/src/soc/sifive/fu540/Makefile.inc
index 4f62f3ed62a1..3c97c08191da 100644
--- a/src/soc/sifive/fu540/Makefile.inc
+++ b/src/soc/sifive/fu540/Makefile.inc
@@ -15,13 +15,13 @@ ifeq ($(CONFIG_SOC_SIFIVE_FU540),y)
bootblock-y += uart.c
bootblock-y += clint.c
-bootblock-y += media.c
+bootblock-y += spi.c
bootblock-y += bootblock.c
bootblock-y += clock.c
romstage-y += uart.c
romstage-y += clint.c
-romstage-y += media.c
+romstage-y += spi.c
romstage-y += sdram.c
romstage-y += cbmem.c
romstage-y += otp.c
@@ -29,7 +29,7 @@ romstage-y += clock.c
ramstage-y += uart.c
ramstage-y += clint.c
-ramstage-y += media.c
+ramstage-y += spi.c
ramstage-y += sdram.c
ramstage-y += cbmem.c
ramstage-y += otp.c