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| author | Xiang Wang <wxjstz@126.com> | 2018-10-11 17:30:37 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-05 09:03:40 +0000 |
| commit | 7c9540ea1d46a776ec92b58f99074f51b430f9bb (patch) | |
| tree | dc9b3d25062791f40edd72ddcccaa3dd0171b85c /src/soc/sifive/fu540/clint.c | |
| parent | c85f9c589726caba41970d5fbdadd8a147dd7956 (diff) | |
| download | coreboot-7c9540ea1d46a776ec92b58f99074f51b430f9bb.tar.gz coreboot-7c9540ea1d46a776ec92b58f99074f51b430f9bb.tar.bz2 coreboot-7c9540ea1d46a776ec92b58f99074f51b430f9bb.zip | |
riscv: add support smp_pause / smp_resume
See https://doc.coreboot.org/arch/riscv/ we know that we need to execute
smp_pause at the start of each stage and smp_resume at the end of each
stage.
Change-Id: I6f8159637bfb15f54f0abeb335de2ba6e9cf82fb
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/29023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Diffstat (limited to 'src/soc/sifive/fu540/clint.c')
| -rw-r--r-- | src/soc/sifive/fu540/clint.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/soc/sifive/fu540/clint.c b/src/soc/sifive/fu540/clint.c index 00aec1ab37a3..fb4b97fbb384 100644 --- a/src/soc/sifive/fu540/clint.c +++ b/src/soc/sifive/fu540/clint.c @@ -14,9 +14,9 @@ */ #include <mcall.h> +#include <stdint.h> #include <arch/io.h> #include <soc/addressmap.h> -#include <soc/clint.h> void mtime_init(void) { @@ -27,6 +27,5 @@ void mtime_init(void) void set_msip(int hartid, int val) { - long hart_id = read_csr(mhartid); - write32((void *)(FU540_CLINT + 4 * hart_id), !!val); + write32((void *)(FU540_CLINT + 4 * (uintptr_t)hartid), !!val); } |