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authorFurquan Shaikh <furquan@google.com>2020-06-11 11:59:07 -0700
committerFurquan Shaikh <furquan@google.com>2020-06-13 06:49:23 +0000
commit46514c2b877c29c2d7c2061a9785736e270c0c62 (patch)
tree2f78550192bce548139ef49fdac6623dad578703 /src/soc/sifive/fu540/memlayout.ld
parent00148bba7146318e2e815d8c13e33278f63814c9 (diff)
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treewide: Add Kconfig variable MEMLAYOUT_LD_FILE
This change defines a Kconfig variable MEMLAYOUT_LD_FILE which allows SoC/mainboard to provide a linker file for the platform. x86 already provides a default memlayout.ld under src/arch/x86. With this new Kconfig variable, it is possible for the SoC/mainboard code for x86 to provide a custom linker file as well. Makefile.inc is updated for all architectures to use this new Kconfig variable instead of assuming memlayout.ld files under a certain path. All non-x86 boards used memlayout.ld under mainboard directory. However, a lot of these boards were simply including the memlayout from SoC. So, this change also updates these mainboards and SoCs to define the Kconfig as required. BUG=b:155322763 TEST=Verified that abuild with --timeless option results in the same coreboot.rom image for all boards. Change-Id: I6a7f96643ed0519c93967ea2c3bcd881a5d6a4d6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42292 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/sifive/fu540/memlayout.ld')
-rw-r--r--src/soc/sifive/fu540/memlayout.ld27
1 files changed, 27 insertions, 0 deletions
diff --git a/src/soc/sifive/fu540/memlayout.ld b/src/soc/sifive/fu540/memlayout.ld
new file mode 100644
index 000000000000..fd63dc0b452b
--- /dev/null
+++ b/src/soc/sifive/fu540/memlayout.ld
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <memlayout.h>
+#include <soc/addressmap.h>
+
+#include <arch/header.ld>
+
+#define L2LIM_START(addr) SYMBOL(l2lim, addr)
+#define L2LIM_END(addr) SYMBOL(el2lim, addr)
+
+SECTIONS
+{
+ L2LIM_START(FU540_L2LIM)
+ BOOTBLOCK(FU540_L2LIM, 64K)
+ CAR_STACK(FU540_L2LIM + 64K, 20K)
+ PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 84K, 8K)
+ FMAP_CACHE(FU540_L2LIM + 92K, 2K)
+ ROMSTAGE(FU540_L2LIM + 128K, 128K)
+ PRERAM_CBFS_CACHE(FU540_L2LIM + 256K, 128K)
+ L2LIM_END(FU540_L2LIM + 2M)
+
+ DRAM_START(FU540_DRAM)
+ REGION(opensbi, FU540_DRAM, 128K, 4K)
+ RAMSTAGE(FU540_DRAM + 128K, 256K)
+ MEM_STACK(FU540_DRAM + 448K, 20K)
+ POSTRAM_CBFS_CACHE(FU540_DRAM + 512K, 32M - 512K)
+}