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| author | Philipp Hug <philipp@hug.cx> | 2018-12-01 18:17:18 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-12-07 11:37:53 +0000 |
| commit | 968a23d2e0afcf3ead23d3075aecc5c6e27211e4 (patch) | |
| tree | 224538a6d842bd87f15ea167c5b75b9a555a8570 /src/soc/sifive/fu540 | |
| parent | 6ee37ef59ddf5e7f005e0aa24541b190384ab87c (diff) | |
| download | coreboot-968a23d2e0afcf3ead23d3075aecc5c6e27211e4.tar.gz coreboot-968a23d2e0afcf3ead23d3075aecc5c6e27211e4.tar.bz2 coreboot-968a23d2e0afcf3ead23d3075aecc5c6e27211e4.zip | |
riscv: fix non-SMP support
Use CONFIG_CPU_MAX which defaults to 1 instead of CONFIG_RISCV_HART_NUM.
The default value of CONFIG_RISCV_HART_NUM was 0 and cause a jump to address 0.
Add a die() call to fail gracefully.
Change-Id: I4e3aa09b787ae0f26a4aae375f4e5fcd745a0a1e
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/c/29993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Xiang Wang <wxjstz@126.com>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Diffstat (limited to 'src/soc/sifive/fu540')
| -rw-r--r-- | src/soc/sifive/fu540/Kconfig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig index 72305d67a9a3..795f51b4d67d 100644 --- a/src/soc/sifive/fu540/Kconfig +++ b/src/soc/sifive/fu540/Kconfig @@ -39,7 +39,7 @@ config RISCV_CODEMODEL string default "medany" -config RISCV_HART_NUM +config MAX_CPUS int default 5 |