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| author | Martin Roth <martin@coreboot.org> | 2021-10-01 14:53:22 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-10-05 18:07:08 +0000 |
| commit | 26f97f9532933da3c1d72a7918c8a24457bbc1c0 (patch) | |
| tree | 8c25279e58ef541fae197ec193f5642a9b21b2d4 /src/soc/sifive | |
| parent | 50863daef8ed75c0cb3dfd375e7622c898de5821 (diff) | |
| download | coreboot-26f97f9532933da3c1d72a7918c8a24457bbc1c0.tar.gz coreboot-26f97f9532933da3c1d72a7918c8a24457bbc1c0.tar.bz2 coreboot-26f97f9532933da3c1d72a7918c8a24457bbc1c0.zip | |
src/soc to src/superio: Fix spelling errors
These issues were found and fixed by codespell, a useful tool for
finding spelling errors.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/sifive')
| -rw-r--r-- | src/soc/sifive/fu540/ux00ddr.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/sifive/fu540/ux00ddr.h b/src/soc/sifive/fu540/ux00ddr.h index 14a628d4415d..cc675080dcd1 100644 --- a/src/soc/sifive/fu540/ux00ddr.h +++ b/src/soc/sifive/fu540/ux00ddr.h @@ -82,14 +82,14 @@ static inline void ux00ddr_mask_mc_init_complete_interrupt(size_t ahbregaddr) { static inline void ux00ddr_mask_outofrange_interrupts(size_t ahbregaddr) { // Mask off Bit 8, Bit 2 and Bit 1 of Interrupt Status - // Bit [2] Multiple accesses outside the defined PHYSICAL memory space have occured - // Bit [1] A memory access outside the defined PHYSICAL memory space has occured + // Bit [2] Multiple accesses outside the defined PHYSICAL memory space have occurred + // Bit [1] A memory access outside the defined PHYSICAL memory space has occurred _REG32(136<<2, ahbregaddr) |= ((1<<OUT_OF_RANGE_OFFSET) | (1<<MULTIPLE_OUT_OF_RANGE_OFFSET)); } static inline void ux00ddr_mask_port_command_error_interrupt(size_t ahbregaddr) { // Mask off Bit 7 of Interrupt Status - // Bit [7] An error occured on the port command channel + // Bit [7] An error occurred on the port command channel _REG32(136<<2, ahbregaddr) |= (1<<PORT_COMMAND_CHANNEL_ERROR_OFFSET); } |