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| author | Patrick Georgi <patrick@coreboot.org> | 2023-10-07 11:16:43 +0200 |
|---|---|---|
| committer | Patrick Georgi <patrick@coreboot.org> | 2023-10-11 12:08:22 +0000 |
| commit | 42f15054b178efe9a4d1c8a4e0c203d1aa4aad01 (patch) | |
| tree | e1702953813d9c5c0930be4aca3d95b2aeecde00 /src/soc/sifive | |
| parent | c666a916112aece345da57a0b4f3bafc43234ee7 (diff) | |
| download | coreboot-42f15054b178efe9a4d1c8a4e0c203d1aa4aad01.tar.gz coreboot-42f15054b178efe9a4d1c8a4e0c203d1aa4aad01.tar.bz2 coreboot-42f15054b178efe9a4d1c8a4e0c203d1aa4aad01.zip | |
memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere
This is in preparation of a larger heap. I went for 2MB because why not?
Change-Id: I51f999a10ba894a7f2f5fce224d30bf914107c38
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/sifive')
| -rw-r--r-- | src/soc/sifive/fu540/memlayout.ld | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/sifive/fu540/memlayout.ld b/src/soc/sifive/fu540/memlayout.ld index 73faa4b4e808..8fc875dba711 100644 --- a/src/soc/sifive/fu540/memlayout.ld +++ b/src/soc/sifive/fu540/memlayout.ld @@ -22,7 +22,7 @@ SECTIONS DRAM_START(FU540_DRAM) REGION(opensbi, FU540_DRAM, 128K, 4K) - RAMSTAGE(FU540_DRAM + 128K, 256K) - MEM_STACK(FU540_DRAM + 448K, 20K) - POSTRAM_CBFS_CACHE(FU540_DRAM + 512K, 32M - 512K) + RAMSTAGE(FU540_DRAM + 128K, 2M) + MEM_STACK(FU540_DRAM + 128K + 2M, 20K) + POSTRAM_CBFS_CACHE(FU540_DRAM + 3M, 29M) } |