diff options
| author | Philipp Hug <philipp@hug.cx> | 2018-09-10 19:32:23 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-09-10 20:36:45 +0000 |
| commit | 2cf9990ec8776d5a514e188144c57ee42428e815 (patch) | |
| tree | 3b4c27e894ea04b437b99f536fad05285a22a63b /src/soc/ucb/riscv | |
| parent | 7f60d24fbda48f982c413528df71d4f56e8df5bf (diff) | |
| download | coreboot-2cf9990ec8776d5a514e188144c57ee42428e815.tar.gz coreboot-2cf9990ec8776d5a514e188144c57ee42428e815.tar.bz2 coreboot-2cf9990ec8776d5a514e188144c57ee42428e815.zip | |
soc/sifive/fu540: Makefile: include mtime_init in ramstage
Fix compilation issue
clint.c/mtime.c is needed as well in ramstage due to CR 28372 and 28355
Change-Id: I7c7768744a165b97978bb8f7f95acf7b32ca4aa4
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28551
Tested-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/ucb/riscv')
| -rw-r--r-- | src/soc/ucb/riscv/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/ucb/riscv/Makefile.inc b/src/soc/ucb/riscv/Makefile.inc index 16225c0968c1..a10f3aae4c0b 100644 --- a/src/soc/ucb/riscv/Makefile.inc +++ b/src/soc/ucb/riscv/Makefile.inc @@ -3,5 +3,6 @@ ifeq ($(CONFIG_SOC_UCB_RISCV),y) bootblock-y += mtime.c romstage-y += cbmem.c ramstage-y += cbmem.c +ramstage-y += mtime.c endif |