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| author | Arthur Heymans <arthur@aheymans.xyz> | 2023-11-14 13:30:10 +0100 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-01-12 09:46:44 +0000 |
| commit | 58831615c30a58813aa938a938eb254f4759157c (patch) | |
| tree | 1716b0d8324983b55abeeb646d68b113c160d5c6 /src/soc/ucb/riscv | |
| parent | cf6d9ac22f2afd96b6f0b33cb67abb9a7828839d (diff) | |
| download | coreboot-58831615c30a58813aa938a938eb254f4759157c.tar.gz coreboot-58831615c30a58813aa938a938eb254f4759157c.tar.bz2 coreboot-58831615c30a58813aa938a938eb254f4759157c.zip | |
soc/intel/xeon_sp: Allocate resources above 4G
This makes sure that prefetchable mem64 memory gets allocated above 4G
which allows non prefetchable resources to be allocated in the tight
window below 4G.
TEST=intel/archercity CRB
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I27d4f9ce91c12ed4ab3b2f18f2a92b742115d275
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79058
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/ucb/riscv')
0 files changed, 0 insertions, 0 deletions