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| author | Xiang Wang <wxjstz@126.com> | 2018-07-12 14:56:05 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-07-17 18:09:43 +0000 |
| commit | 5fed693a52ed9746900ce58ec12a2b245f08202e (patch) | |
| tree | 29bc3c68250a8365e0c25134f4383b07d29bb93f /src/soc/ucb/riscv | |
| parent | 745e58a5ee50373276924349524a2594599e8bb5 (diff) | |
| download | coreboot-5fed693a52ed9746900ce58ec12a2b245f08202e.tar.gz coreboot-5fed693a52ed9746900ce58ec12a2b245f08202e.tar.bz2 coreboot-5fed693a52ed9746900ce58ec12a2b245f08202e.zip | |
riscv: add support for modifying compiler options
Each HART of a SoC like fu540 supports a different ISA. In order for the
coreboot's code can run on each core, need to modify the compile options.
So add this code.
Change-Id: Ie33edc175e612846d4a74f3cbf7520d4145cb68b
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/27442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Diffstat (limited to 'src/soc/ucb/riscv')
| -rw-r--r-- | src/soc/ucb/riscv/Kconfig | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/ucb/riscv/Kconfig b/src/soc/ucb/riscv/Kconfig index ff50f6f8357d..2a73f5c28437 100644 --- a/src/soc/ucb/riscv/Kconfig +++ b/src/soc/ucb/riscv/Kconfig @@ -10,4 +10,16 @@ config SOC_UCB_RISCV if SOC_UCB_RISCV +config RISCV_ARCH + string + default "rv64imafd" + +config RISCV_ABI + string + default "lp64d" + +config RISCV_CODEMODEL + string + default "medany" + endif |