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| author | Angel Pons <th3fanbus@gmail.com> | 2021-10-11 13:53:15 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-10-12 17:37:26 +0000 |
| commit | 0c7a25069e0d855013d082a87b5810c60336acb9 (patch) | |
| tree | e451e7cb9ee146178c88ff5f70ad0d25be790e53 /src/soc | |
| parent | 4d794bd4ec669966803a260c0056808ead4bb408 (diff) | |
| download | coreboot-0c7a25069e0d855013d082a87b5810c60336acb9.tar.gz coreboot-0c7a25069e0d855013d082a87b5810c60336acb9.tar.bz2 coreboot-0c7a25069e0d855013d082a87b5810c60336acb9.zip | |
soc/intel/cannonlake: Lock PKG_CST_CONFIG_CONTROL MSR
Set PKG_CST_CONFIG_CONTROL MSR bit 15 to make bits 15:0 read-only.
Change-Id: Ia196906d3c2636742ae90160a224354e8df7863a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/cannonlake/cpu.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 821694eb5331..99fcadd58185 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -62,8 +62,9 @@ static void configure_c_states(const config_t *const cfg) msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); if (cfg->max_package_c_state && (msr.lo & 0xf) >= cfg->max_package_c_state) { msr.lo = (msr.lo & ~0xf) | ((cfg->max_package_c_state - 1) & 0xf); - wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); } + msr.lo |= CST_CFG_LOCK_MASK; + wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); /* C-state Interrupt Response Latency Control 0 - package C3 latency */ msr.hi = 0; |