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| author | Felix Held <felix-coreboot@felixheld.de> | 2023-04-26 16:04:44 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-04-28 20:13:47 +0000 |
| commit | 0de53be394deefe093b79c3b85f453023173fa98 (patch) | |
| tree | ea5b0a2587874a4b134d4823678df8c2286f058e /src/soc | |
| parent | 4c98dfb4e3c3e133411a6c857b33e383a4f250d7 (diff) | |
| download | coreboot-0de53be394deefe093b79c3b85f453023173fa98.tar.gz coreboot-0de53be394deefe093b79c3b85f453023173fa98.tar.bz2 coreboot-0de53be394deefe093b79c3b85f453023173fa98.zip | |
soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct number of PCI buses
This ports commit 8c28e51a16e1 ("soc/amd/picasso: fix host bridge bus
numbers") back to Stoneyridge so that the correct number of PCI buses
gets reported from PCI0's _CRS method. The MCFG ACPI table already had
the correct last bus number.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I40121ab0e0438281192b6a0bec8dbecdc1749379
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index 6a7ed2ea429e..dad8aaa2cfc9 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -111,6 +111,11 @@ Method(_CRS, 0) { Local0 -= TOM1 MM1L = Local0 + CreateWordField(CRES, ^PSB0._MAX, BMAX) + CreateWordField(CRES, ^PSB0._LEN, BLEN) + BMAX = CONFIG_ECAM_MMCONF_BUS_NUMBER - 1 + BLEN = CONFIG_ECAM_MMCONF_BUS_NUMBER + Return (CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */ |