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authorElyes Haouas <ehaouas@noos.fr>2022-02-16 16:48:48 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-02-17 17:12:49 +0000
commit0ff941dd2029494817ab4e8778574cbbb44e298a (patch)
tree0e9706b4125ffc10974155b26cda4886e380c9e4 /src/soc
parent5b0103f9b507f9825a383d31376f4ac7762af738 (diff)
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src/soc: Remove space before tab
Spaces before tabs are not allowed. Change-Id: I0d2c55c2e0108e59facd92b2e2c0f6c418ef6db0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62055 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/amd/cezanne/acpi/pci0.asl2
-rw-r--r--src/soc/amd/common/acpi/upep.asl2
-rw-r--r--src/soc/amd/sabrina/acpi/pci0.asl2
-rw-r--r--src/soc/intel/common/block/acpi/acpi/globalnvs.asl2
-rw-r--r--src/soc/intel/common/block/fast_spi/Makefile.inc2
5 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/amd/cezanne/acpi/pci0.asl b/src/soc/amd/cezanne/acpi/pci0.asl
index 08ccbe6cf031..7bd434a7f802 100644
--- a/src/soc/amd/cezanne/acpi/pci0.asl
+++ b/src/soc/amd/cezanne/acpi/pci0.asl
@@ -3,7 +3,7 @@
Device(PCI0) {
Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */
Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */
- External(TOM1, IntObj) /* Generated by root_complex.c */
+ External(TOM1, IntObj) /* Generated by root_complex.c */
Method(_BBN, 0, NotSerialized) {
Return(Zero) /* Bus number = 0 */
diff --git a/src/soc/amd/common/acpi/upep.asl b/src/soc/amd/common/acpi/upep.asl
index b44ed43b23cc..d8ea30f09faf 100644
--- a/src/soc/amd/common/acpi/upep.asl
+++ b/src/soc/amd/common/acpi/upep.asl
@@ -3,7 +3,7 @@
#define PEPD_DSM_UUID "e3f32452-febc-43ce-9039-932122d37721"
#define PEPD_DSM_LPI_ENUM_FUNCTIONS 0
#define PEPD_DSM_LPI_ADDITIONAL_FUNCTIONS 1
-#define PEPD_DSM_LPI_GET_DEVICE_CONSTRAINTS 1
+#define PEPD_DSM_LPI_GET_DEVICE_CONSTRAINTS 1
#define PEPD_DSM_NOTIFICATIONS_UUID "11e00d56-ce64-47ce-837b-1f898f9aa461"
#define PEPD_DSM_NOTIFICATION_ENUM_FUNCTIONS 0
diff --git a/src/soc/amd/sabrina/acpi/pci0.asl b/src/soc/amd/sabrina/acpi/pci0.asl
index 853c686de068..e729ba38ff19 100644
--- a/src/soc/amd/sabrina/acpi/pci0.asl
+++ b/src/soc/amd/sabrina/acpi/pci0.asl
@@ -5,7 +5,7 @@
Device(PCI0) {
Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */
Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */
- External(TOM1, IntObj) /* Generated by root_complex.c */
+ External(TOM1, IntObj) /* Generated by root_complex.c */
Method(_BBN, 0, NotSerialized) {
Return(Zero) /* Bus number = 0 */
diff --git a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
index ab63a5c407d1..bb7ab0c41c97 100644
--- a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
+++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
@@ -24,5 +24,5 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
UIOR, 8, // 0x2f - UART debug controller init on S3 resume
A4GB, 64, // 0x30 - 0x37 Base of above 4GB MMIO Resource
A4GS, 64, // 0x38 - 0x3f Length of above 4GB MMIO Resource
- , 64, // 0x40 - 0x47 Hest log buffer (used in SMM, not ASL code)
+ , 64, // 0x40 - 0x47 Hest log buffer (used in SMM, not ASL code)
}
diff --git a/src/soc/intel/common/block/fast_spi/Makefile.inc b/src/soc/intel/common/block/fast_spi/Makefile.inc
index 4fe616377313..ff8517d64eda 100644
--- a/src/soc/intel/common/block/fast_spi/Makefile.inc
+++ b/src/soc/intel/common/block/fast_spi/Makefile.inc
@@ -48,7 +48,7 @@ check-fmap-16mib-crossing: $(obj)/fmap_config.h
flash_offset=$$(fmap_get FMAP_SECTION_FLASH_START); \
flash_size=$$(fmap_get FMAP_SECTION_FLASH_SIZE); \
if [ $$((flash_size)) -le $$((0x1000000)) ]; then \
- exit; \
+ exit; \
fi; \
bios_16M_boundary=$$((flash_size-0x1000000)); \
for x in $$(grep "FMAP_TERMINAL_SECTIONS" < $< | cut -d\" -f2); \