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| author | Martin Roth <gaumless@gmail.com> | 2023-03-06 17:43:13 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-08 22:18:12 +0000 |
| commit | 1011cf2375bfe099fa4c3c8eef469eaa7021c98a (patch) | |
| tree | d82b21a06b0f4c425c924b8f6dab29bd1b948d4a /src/soc | |
| parent | d91625da60406d7d6b40d3d08155100f2705af73 (diff) | |
| download | coreboot-1011cf2375bfe099fa4c3c8eef469eaa7021c98a.tar.gz coreboot-1011cf2375bfe099fa4c3c8eef469eaa7021c98a.tar.bz2 coreboot-1011cf2375bfe099fa4c3c8eef469eaa7021c98a.zip | |
soc/amd/common/psp: Only set SPL fuses if an SPL file is present
Use the presence of an SPL (Software Patch Level) file to trigger the
function that reads and writes the SPL fuses. The current Kconfig
option will be used to decide to write the fuses. This allows us to
see the state of the SPL update bit which determines whether or not
SPL fusing is allowed and needed before enabling the fusing.
- Refactor a bit to prepare for following changes.
- Update phrasing
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I7bd2798b984673a4bd3c72f3cab52f1c9a786c67
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/common/block/psp/psp_def.h | 1 | ||||
| -rw-r--r-- | src/soc/amd/common/block/psp/psp_gen2.c | 24 |
2 files changed, 16 insertions, 9 deletions
diff --git a/src/soc/amd/common/block/psp/psp_def.h b/src/soc/amd/common/block/psp/psp_def.h index 1d87878c03e5..a1eceab27854 100644 --- a/src/soc/amd/common/block/psp/psp_def.h +++ b/src/soc/amd/common/block/psp/psp_def.h @@ -108,5 +108,6 @@ void psp_print_cmd_status(int cmd_status, struct mbox_buffer_header *header); int send_psp_command(u32 command, void *buffer); uint32_t soc_read_c2p38(void); +void psp_set_spl_fuse(void *unused); #endif /* __AMD_PSP_DEF_H__ */ diff --git a/src/soc/amd/common/block/psp/psp_gen2.c b/src/soc/amd/common/block/psp/psp_gen2.c index 65043e5245b8..92063d6cdb05 100644 --- a/src/soc/amd/common/block/psp/psp_gen2.c +++ b/src/soc/amd/common/block/psp/psp_gen2.c @@ -114,25 +114,31 @@ uint32_t soc_read_c2p38(void) return smn_read32(SMN_PSP_PUBLIC_BASE + CORE_2_PSP_MSG_38_OFFSET); } -static void psp_set_spl_fuse(void *unused) +void psp_set_spl_fuse(void *unused) { - if (!CONFIG(SOC_AMD_COMMON_BLOCK_PSP_FUSE_SPL)) - return; - int cmd_status = 0; struct mbox_cmd_late_spl_buffer buffer = { .header = { .size = sizeof(buffer) } }; + uint32_t c2p38 = soc_read_c2p38(); - if (soc_read_c2p38() & CORE_2_PSP_MSG_38_FUSE_SPL) { - printk(BIOS_DEBUG, "PSP: Fuse SPL requested\n"); - cmd_status = send_psp_command(MBOX_BIOS_CMD_SET_SPL_FUSE, &buffer); - psp_print_cmd_status(cmd_status, NULL); + if (c2p38 & CORE_2_PSP_MSG_38_FUSE_SPL) { + printk(BIOS_DEBUG, "PSP: SPL Fusing may be updated.\n"); } else { - printk(BIOS_DEBUG, "PSP: Fuse SPL not requested\n"); + printk(BIOS_DEBUG, "PSP: SPL Fusing not currently required.\n"); + return; } + + if (!CONFIG(SOC_AMD_COMMON_BLOCK_PSP_FUSE_SPL)) + return; + + printk(BIOS_DEBUG, "PSP: SPL Fusing Update Requested.\n"); + cmd_status = send_psp_command(MBOX_BIOS_CMD_SET_SPL_FUSE, &buffer); + psp_print_cmd_status(cmd_status, NULL); } +#if CONFIG(HAVE_SPL_FILE) BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_ENTRY, psp_set_spl_fuse, NULL); +#endif |